The next gold mine for semiconductor equipment lies in packaging factories.
Advanced packaging has become a hot topic in the semiconductor market recently. On one hand, ASML, the leading lithography machine manufacturer, has officially targeted advanced packaging. On the other hand, Broadcom has started shipping the first SoC chip of its 3.5D XDSiP advanced packaging platform.
Behind these actions lies a clear industry consensus: Moore's Law has entered the second half, and the path of relying solely on process miniaturization has become increasingly narrow. Advanced packaging is becoming the key growth driver for the semiconductor industry in the next decade and a new arena for core industry competition.
To understand the inevitability of this transformation, we need to first penetrate the two core dilemmas faced by the chip industry under the bottleneck of advanced processes.
Chip Miniaturization Reaches a Dead End
Over the past half - century, the core narrative of the semiconductor industry has always revolved around "transistor miniaturization." Each iteration of the process technology (from 28nm to 7nm, then to 3nm and 2nm) essentially involves reducing the transistor size to integrate more transistors on a single chip wafer, thereby achieving the "double dividends" of performance improvement and power consumption reduction. This logic has supported the industry's high - speed growth for decades and has become the core driving force for the development of the chip industry.
However, today, this well - proven path has hit an insurmountable ceiling.
From a physical perspective, when the transistor size approaches the atomic level, traditional silicon - based CMOS technology faces fundamental challenges: the problem of transistor gate leakage is becoming increasingly serious, the quantum tunneling effect leads to a significant decline in chip stability, and it is difficult to optimize signal transmission delay. Even with the current most advanced 3nm process, the transistor density has approached the physical limit, and the performance gain from further miniaturization is showing marginal diminishing returns - for every nanometer of progress, the difficulty of technological breakthrough increases exponentially.
From a cost perspective, advanced chip manufacturing relies on core equipment such as extreme ultraviolet lithography (EUV), and only a few global companies can master EUV technology. The procurement cost of the equipment exceeds $150 million per unit. At the same time, process miniaturization has extremely strict requirements for the purity of raw materials and the cleanliness of the production environment, further driving up the operating costs of wafer fabs. This can be seen from TSMC's wafer quotes:
The constraints of physical limits and the heavy economic costs jointly announce the end of the era of "solely relying on process miniaturization." The bottleneck in the technological path forces the industry to break out of the "size competition" and find new ways to improve performance.
Advanced packaging is the best answer to these two dilemmas.
The Battlefield of Advanced Packaging is Clearly Defined
The core logic of advanced packaging is "heterogeneous integration and system reconstruction" - it no longer focuses on the process improvement of a single chip but achieves the efficient integration of multiple chips and heterogeneous chips through packaging - level technological innovation, using system - level global optimization to make up for the performance shortcomings of a single chip.
Currently, the global mainstream advanced packaging technologies are mainly divided into four major routes, each with its own clear core battlefield, core contradictions to be solved, and corresponding industrial patterns.
The first route is 2.5D/3D packaging, which is also the core carrier of current high - end computing power. As a necessary technology for large AI models, HPC, and high - end GPUs, 2.5D/3D packaging focuses on achieving extreme interconnection bandwidth and ultra - low latency, directly determining the performance release of high - end computing power chips.
Among them, 2.5D packaging achieves high - density interconnection through an interposer. The interposer is mostly made of silicon or glass materials, and a fine interconnection network is constructed through the redistribution layer (RDL) and through - silicon vias (TSV). The chips are first bonded to the interposer and then connected to the substrate through the interposer. The wiring density of the silicon interposer is much higher than that of traditional organic substrates, enabling micron - level line widths and line spacings, significantly shortening the interconnection distance between chips, increasing the signal bandwidth by 3 - 5 times, and reducing power consumption by about 40%. The glass interposer, with its lower dielectric loss and better thermal stability, has become the core material direction for the next - generation 2.5D packaging. Typical applications include AI accelerator cards, high - end GPUs (such as NVIDIA H100), and data center chips. Technologies such as TSMC's CoWoS and Intel's EMIB are mature representatives of 2.5D packaging and have achieved large - scale mass production.
3D packaging completely breaks the planar limit and achieves a qualitative leap in integration density through "vertical stacking." It is the core form of high - end packaging. Its core logic is to vertically stack multiple chips (logic chips, memory chips, etc.) and achieve direct inter - layer interconnection through through - silicon vias or hybrid bonding technology without the need for an interposer to transfer. This is also the essential difference between 3D and 2.5D packaging. Intel's Foveros and Samsung's X - Cube technologies have been implemented and are the core directions for the next - generation supercomputers and flagship AI chips.
Although these technologies are leading, they face problems such as high costs and complex manufacturing processes, and are also restricted by the capacity dependence and ecological barriers caused by the highly concentrated supply chain (especially the tight production capacity of TSMC's CoWoS).
The second route is Chiplet packaging. Its core is to split a large SoC into multiple functional chiplets, select the optimal process for foundry as needed, and then achieve the complete function through packaging integration. For example, the most critical modules (such as the computing core) use advanced processes, while modules such as I/O and storage that are less sensitive to the process use mature processes, thus achieving a balance between overall performance and cost. AMD has rapidly increased its share in the x86 CPU market with its Zen architecture Chiplet solution. In China, leading companies such as Changjiang Electronics Technology and Tongfu Microelectronics have achieved large - scale breakthroughs, and multiple domestic Chiplet architecture chips have been launched.
Although the Chiplet technology enables flexible design and cost optimization, it faces challenges such as high design complexity caused by multi - chiplet integration, difficulty in unifying interconnection standards, and potential system - level collaborative verification risks.
The third route is fan - out packaging (Fan - Out). If 2.5D/3D is exclusive to the high - end, fan - out packaging is the preferred solution for achieving a balance between high performance and cost. It abandons traditional substrates and lead frames and directly manufactures the redistribution layer (RDL) at the wafer level. This not only significantly reduces the packaging volume and improves the heat dissipation efficiency but also provides a more competitive cost advantage than 2.5D packaging.
Although fan - out packaging has outstanding cost - performance, it still lags behind 2.5D/3D packaging in terms of electrical performance and design flexibility when facing the requirements of extreme I/O density and ultra - large - scale integration.
The fourth route is SiP system - level packaging. SiP is the first choice for fragmented scenarios such as consumer electronics, wearables, the Internet of Things, and in - vehicle electronics, mainly meeting the requirements of "small size, full function, and fast implementation." By integrating multiple types of chips such as processors, storage, sensors, and RF into a single package, SiP achieves a complete system function, with the advantages of a short R & D cycle, strong adaptability, and high integration. It is a cost - effective solution for fragmented demand scenarios. Apple's iPhone and AirPods series have widely adopted SiP, and domestic in - vehicle and IoT manufacturers have also rapidly achieved product mass production relying on SiP.
Although not the most advanced in terms of parameters, SiP is the advanced packaging solution with the widest application range and closest to the end - market.
Lithography Machines are Making a Splash in the Packaging Market
It can be seen that current advanced packaging technologies have completely deviated from the traditional "assembly" category and entered the advanced stage of "micro - nano manufacturing." Lithography technology is the core support for this transformation.
From a technical perspective, wafer - level packaging (WLP) directly performs packaging on the entire wafer, requiring lithography technology to define the wiring layer with a precision requirement reaching the nanometer level. In Chiplet packaging technology, the "interconnection" of different chiplets requires ultra - fine lines, and lithography technology must be used to achieve high - precision manufacturing of "bumps" and "redistribution layers." In 3D IC packaging technology, after the chips are vertically stacked, the processing of through - silicon vias (TSV) also requires lithography for auxiliary positioning.
The current back - end lithography market has long been dominated by Canon. Now, the competition in this field is becoming increasingly fierce. It is reported that ASML has started supplying its advanced packaging lithography system Twinscan XT:260, with the first shipments starting at the end of 2025. The XT:260 has a higher throughput, claiming a productivity up to four times that of traditional systems. The device can handle substrates with a thickness between 0.775 and 1.7 millimeters and can alleviate the warpage of up to 1 millimeter caused by multi - chip mounting.
Nikon plans to enter this market in March 2027, forming a market pattern of competition among Canon, ASML, and Nikon. The competition in technical routes and cost control will intensify further.
The explosive growth of AI computing power demand has become the core driving force for the demand for packaging lithography equipment. AI processors deeply integrate GPUs and HBM through 2.5D/3D packaging to break through the storage bandwidth bottleneck. This architecture requires nanometer - level precision for the interposer lines. The rapid expansion of TSMC's CoWoS packaging production capacity confirms this trend: its monthly production capacity has increased from 35,000 wafers in 2024 to 70,000 wafers at the end of 2025 and is expected to reach 130,000 wafers at the end of 2026. The concentrated orders from leading customers such as NVIDIA and AMD have directly driven a surge in the demand for high - precision interposer lithography systems. It is worth noting that as the packaging size continues to increase, manufacturers are shifting from traditional circular silicon wafers to rectangular substrates to reduce the material loss rate, which places higher requirements on the substrate adaptability and process flexibility of lithography equipment.
Hybrid Bonding Equipment, Another Core Pillar of Advanced Packaging
While lithography technology dominates the line definition, hybrid bonding equipment is emerging as another key increment in the advanced packaging boom with the "interconnection revolution."
As an upgraded solution to traditional thermocompression bonding and bump bonding, hybrid bonding technology (especially Cu - Cu hybrid bonding) compresses the interconnection pitch from 40μm in traditional solutions to 1 - 2μm through the simultaneous bonding of metals and dielectrics, enabling millions of connection points per square centimeter. This increases the data transmission bandwidth between chips by an order of magnitude, while reducing parasitic resistance and power consumption. It has become a must - have technology for high - end packaging scenarios such as 3D IC stacking and HBM manufacturing. The above - mentioned four advanced packaging technologies also have clear requirements for hybrid bonding technology. For example, 3D packaging, as its core application scenario, relies on hybrid bonding to achieve direct inter - layer interconnection in the "vertical stacking" architecture. In the process of Chiplet packaging moving towards high - end, processors such as AMD use hybrid bonding to solve the bandwidth bottleneck between chiplets.
It is reported that ASML is developing hybrid bonding equipment and has established technical cooperation with two suppliers, Prodrive and VDL - ETG. These two companies previously provided core components of the magnetic levitation system for ASML's EUV lithography machines, and their technical accumulation will provide key support for the precise motion control of the new packaging equipment.
Marco Pieters, ASML's Chief Technology Officer, previously publicly stated that equipment innovation in the packaging process will become a new growth driver for the semiconductor industry. Especially, hybrid bonding technology can achieve denser interconnections between chips, which places extremely high requirements on equipment precision. If the hybrid bonding equipment is successfully developed, it will form a synergistic effect with ASML's existing product line, enabling it to cover the entire industrial chain equipment supply from wafer manufacturing to packaging and testing.
The synergy between hybrid bonding and lithography technology forms the core manufacturing closed - loop of advanced packaging: lithography technology is responsible for the precise definition of lines and bonding pads, and hybrid bonding equipment achieves high - density interconnection between chips. Together, they support the advanced packaging system of "micro - nano manufacturing + heterogeneous integration."
3.5D Packaging: The Giants are All In
Facing the computing demand brought by AI, semiconductor giants such as Broadcom, AMD, Intel, and Samsung are jointly defining 3.5D packaging with their respective core technology solutions.
As early as 2023, AMD released the MI300 series of AI accelerators that attracted industry attention, becoming the first computing giant to introduce 3.5D packaging technology into mass production. AMD's 3.5D packaging essentially integrates and innovates TSMC's two cutting - edge technologies: it uses the SoIC 3D stacking technology based on Cu - Cu hybrid bonding to vertically stack GPU computing chips or CPU chips on the I/O chip (IOD), achieving a more than 15 - fold increase in interconnection density and extreme energy efficiency. At the same time, it relies on the CoWoS 2.5D silicon interposer to achieve high - density side - by - side interconnection between multiple 3D stacking modules and HBM3 memory. This composite architecture of 3D stacked computing chips + 2.5D integrated memory and I/O is what AMD defines as "3.5D packaging."
Broadcom also recently announced an important development: a custom - computing SoC based on its XDSiP 3.5D platform and using the 2nm process has been officially delivered to Fujitsu for use in AI supercomputing clusters. This technology was launched by Broadcom in 2024, and its core "killer feature" is the use of face - to - face (F2F) hybrid copper bonding technology.
Different from the traditional "face - to - back stacking (F2B)", Broadcom directly bonds the 2nm computing chip and the 5nm SRAM cache chip "face - to - face." This atomic - level copper - copper connection enables tens of thousands of interconnection points per square millimeter, significantly increasing the interconnection density between chips and significantly reducing interface power consumption. This high - density, low - power interconnection capability provides a foundation for computing - intensive applications. It is reported that the F2F HCB technology used in 3.5D XDSiP is likely to be the exclusive implementation solution for TSMC's SoIC - X (bump - less) stacking technology. Similar to AMD's solution, although this solution uses Broadcom's self - developed design architecture and automated process, it is defined as "3.5D" packaging because it integrates both 2.5D integration and 3D stacking technologies.
Samsung's advanced packaging technologies are mainly divided into two categories: I - Cube, which belongs to 2.5D packaging, and X - Cube, which belongs to 3DIC. At the same time, Samsung Electronics' Advanced Packaging (AVP) department is also leading the development of "semiconductor 3.3D advanced packaging technology" for application in AI semiconductor chips, with mass production scheduled for the second quarter of 2026. This technology connects logic chips and HBM by installing an RDL interposer instead of a silicon interposer and stacks logic chips on the LLC through 3D stacking technology. Samsung expects that after the commercialization of the new technology, compared with the existing silicon interposer, the performance will not decline, and the cost can be reduced by 22%. Samsung will also introduce "panel - level packaging (PLP)" technology into 3.3D packaging.
Intel is also developing 3.5D packaging technology that combines 3D packaging and 2.5D packaging. Intel Foundry's Advanced System Packaging and Test (Intel Foundry ASAT) technology portfolio includes various technologies such as FCBGA 2D, FCBGA 2D+, EMIB 2.5D, EMIB 3.5D, Foveros 2.5D & 3D, and Foveros Direct 3D. Its EMIB technology series has made important breakthroughs in the field of chip interconnection. The 2.5D version uses the embedded silicon bridge technology, with a minimum line width/line spacing of 10μm / 10μm, and the interconnection density is increased to 1500 connection points/mm². The 3.5D version achieves vertical interconnection through through - silicon via (TSV) technology, with the via diameter controlled at 5μm and an aspect ratio of 10:1, supporting the three - dimensional stacking of up to 4 layers of chips.
It can be seen that in the development of the next