Chip giants have all invested in this optical company.

In December 2024, Ayar Labs, a startup optical chip design company, announced the completion of a $155 million Series D financing round. The list of investors in this round is truly impressive: in addition to the lead investors, Advent Global Opportunities and Light Street Capital, it also includes industry giants such as NVIDIA, AMD, Intel, GlobalFoundries, VentureTech Alliance (a partner of TSMC), and 3M.

Recently, it has received approximately $500 million in financing. The investors include Neuberger Berman, MediaTek, and the Qatar Investment Authority. This round of financing has also pushed the valuation of this low - key company to $3.8 billion.

What on earth enables this startup company, which has only been established for a decade, to win the favor of chip giants such as NVIDIA, Intel, AMD, and MediaTek, making them put aside their differences and jointly invest?

From the MIT Laboratory to a Silicon Valley Unicorn

The story of Ayar Labs began in 2011 with a cross - university research team composed of members from the Massachusetts Institute of Technology (MIT), the University of California, Berkeley, and the University of Colorado. Their research goal was simple: how to break through when the computing power of chips approaches its limit?

At that time, the success of Moore's Law brought an interesting paradox to the computing field - processors were in an idle waiting state most of the time. Chips rely on copper pins to transmit data, but the transmission speed of copper has a physical limit, and the new - generation chip manufacturers are about to reach this limit. As more and more enterprises use machine learning and big data technologies in commercial scenarios, this problem has become even more prominent. The research team found that although the computing power has been expanding rapidly, the expansion speed of the connectivity of electronic communication and the bandwidth of memory cannot keep up. To break through the physical limitations of electronic communication, "light" is needed.

The three core members of this research project - Chen Sun, Mark Wade, and Vladimir Stojanovic - later became the co - founders of Ayar Labs, serving as the Chief Scientist, CEO, and Chief Technology Officer respectively. In 2015, they met the fourth co - founder, Alex Wright - Gladstein, at the MIT Sloan School of Management. This female entrepreneur, who was pursuing an MBA and had previously worked in the clean - technology field, keenly realized that many people could invent great things but didn't know how to bring them to the market.

In the MIT Clean Energy Entrepreneurship Competition, the four of them participated in the competition with the optoelectronic chip technology under the name of OptiBit and won two grand championships, receiving a $275,000 prize. "Having this early funding to pay our meager salaries provided a bit of a buffer before raising venture capital. It really pushed all of us to make up our minds to start a business," Wright - Gladstein recalled.

However, in the first three years of entrepreneurship, Ayar Labs was rejected by hundreds of investors. Although Silicon Valley's rise originated from silicon - chip semiconductors, in the 2010s, deep - tech startups in hardware manufacturing were not very popular. Mark Wade and the team even deliberately avoided mentioning the term "silicon photonics" in their presentations to make it easier for investors to understand their ideas - "Of course, it's a popular term now, but it was a bit too revolutionary back then."

From Sand Hill Road, San Francisco, Palo Alto, to Mountain View, from 9 a.m. to 5 p.m., Mark Wade shuttled around these places looking for investors. From 5 p.m. to midnight, it was the "chip time" for the team. "It was an impressive and incredible period. Looking back, I don't even know how I managed it," Wade said.

Finally, the first to offer an olive branch to Ayar Labs was the Founders Fund founded by Peter Thiel, the co - founder of PayPal. In 2018, Playground Global led a $24 million Series A financing round for Ayar Labs, and the team finally had the capital to accelerate research and development. Although this is a drop in the bucket in semiconductor industry R & D, the team used this capital very carefully. They set up the first batch of computer - aided design servers (CAD servers) in the office and designed the team's first silicon - photonics chip.

"I always knew that chips would eventually reach their physical limits, but I didn't expect AI to give it a push," Mark Wade said. When the company was founded in 2015, they never thought about whether silicon - photonics technology would become a reality or if what they were doing would ever be achieved. They simply wanted to solve the problem of the data - transmission limit in high - performance computing (HPC).

Ten years later, in 2024, Ayar Labs finally waited for its moment. The company has shipped approximately 15,000 devices to some customers and plans to achieve mass production of chips by the middle of 2026. By 2028 and beyond, the annual shipment volume may exceed 100 million units. Today, the team consists of top technical experts from Intel, IBM, Micron, MIT, Berkeley, and Stanford. It has established strategic partnerships with major manufacturers such as GlobalFoundries, Applied Materials, TSMC, Intel, and NVIDIA.

TeraPHY + SuperNova

Before talking about Ayar Labs' technology, let's first discuss the fundamental challenges faced by AI infrastructure.

As the complexity and scale of generative AI models increase exponentially, the demand for large - scale computing clusters is growing. These computing facilities usually need to connect hundreds or even tens of thousands of GPUs and other accelerators. However, the expansion of AI infrastructure is facing a triple dilemma of bandwidth, latency, and power consumption. These challenges are mainly caused by the bottlenecks of traditional copper - based interconnection technologies.

The data - transmission bottleneck is limiting the performance of GPUs, leading to diminishing returns on investment. Specifically, the operating efficiency of a single GPU can reach 80%, but it may drop to 50% when expanded to 64 GPUs and only 30% when further expanded to 256 GPUs. This not only reduces the overall system efficiency but also seriously hinders the comprehensive improvement of data - center performance and limits the progress of AI technology. Rob Ober, the chief platform architect of NVIDIA's data - center products, believes that in the past decade, NVIDIA's accelerated computing has brought a million - fold acceleration to AI. The next million - fold acceleration will require new technologies such as optical I/O to support the bandwidth, power, and scale requirements of future AI/ML workloads and system architectures.

To address this challenge, Ayar Labs has launched the industry's first in - package optical I/O solution, which is centered around two complementary products: the TeraPHY optical I/O chiplet and the SuperNova multi - wavelength light source.

TeraPHY

The TeraPHY optical I/O chiplet is the core technology carrier of Ayar Labs and is also the industry's first in - package monolithic optical I/O chip. It is mainly responsible for the conversion and transmission of optical and electrical signals. It is a miniaturized, low - power, and high - throughput solution that replaces traditional copper backplanes and pluggable optical communications.

The uniqueness of this chip lies in its first - time combination of silicon - photonics technology with standard CMOS manufacturing processes, integrating optical interconnection with electronic GPUs or CPUs in the same package. It can be seamlessly integrated into the customer's system - in - package (SiP) architecture, enabling application - specific integrated circuits (ASICs) to communicate seamlessly over distances from millimeters to kilometers, minimizing signal loss and latency. This is particularly useful for distributed AI systems and cloud - computing environments.

From a technical architecture perspective, TeraPHY contains approximately 70 million transistors and more than 10,000 optical devices and is mainly composed of the following modules:

Grating Coupler Fiber Coupling Array: Responsible for the input and output of optical signals.

Optical Transceiver: Mainly responsible for the modulation and conversion of optical and electrical signals, consisting of micro - ring modulators and micro - ring filters. The former is responsible for modulating the required optical signals, and the latter is responsible for processing the received optical signals. It is worth mentioning that the micro - ring modulator is the core advantage of TeraPHY - it successfully solves the problems of temperature sensitivity and signal stability, achieving accurate output of optical signals at specific wavelengths in the temperature range of 15 - 100°C.

AIB (Advanced Interface Bus): Responsible for the electrical - signal interconnection between chips.

Glue/Crossbar: Serves as a connection bridge between the Optical Transceiver and AIB.

With its modular multi - port design, TeraPHY can support 8 optical channels, equivalent to an x8 PCIe Gen5 link, meeting the demand for large - scale parallel processing of generative AI models. Its total bidirectional bandwidth of 4 Tbps and high - speed transmission capacity of 256 Gbps per port can quickly move data and accelerate the training and inference processes of AI models. Moreover, the bandwidth of this chip may double every few years.

The low - latency performance of 5 ns helps to improve the data - processing speed and optimize the generative AI experience. More importantly, TeraPHY uses a standard UCIe (Universal Chiplet Interconnect Express) electrical interface, which means that "any chip manufacturer can install it and have an optical converter." When one GPU communicates with another, it doesn't even know that it is leaving the package - this transparency is crucial for large - scale deployment.

SuperNova

If TeraPHY is the converter of optical signals, then SuperNova is the producer of light. This remote - light - source independent laser is responsible for accurately emitting photons of multiple wavelengths and can be regarded as a light power source located somewhere outside the ASIC package. In actual deployment, SuperNova works in tandem with TeraPHY.

SuperNova was jointly designed by Ayar Labs and MACOM (one of the top DFB designers) and manufactured by Sivers Photonics, a well - known laser manufacturer in the UK. It is the first multi - wavelength, multi - port light source that complies with the CW - WDM MSA (Coarse Wavelength Division Multiplexing Multi - Source Agreement) standard, supporting the transmission of light of up to 16 wavelengths to 16 optical fibers, achieving another major leap in optical I/O technology.

Each optical fiber can transmit up to 16 wavelengths, so it can drive 256 optical carriers, providing a bidirectional bandwidth of 16 Tbps, meeting the bandwidth requirements of AI workloads. The number of wavelengths is 64 times that of CWDM4 multi - wavelength pluggable optical devices, and multiple wavelengths in a single array simplify the package and reduce the packaging cost, which is an important advantage for large - scale deployment of AI systems.

Moreover, SuperNova complies with the CW - WDM MSA specification and meets the reliability requirements of GR - 468 for optoelectronic devices and pluggable optics. It can be widely used in fields such as AI architecture, high - speed I/O, optical computing, and high - density co - packaged optical devices.

According to Ayar Labs' data, compared with traditional pluggable optical devices and electrical SerDes interconnection methods, its optical I/O solution shows significant advantages:

Bandwidth increased by 5 - 10 times: From hundreds of Gbps in traditional solutions to the 4 - 16 Tbps level.

Energy efficiency increased by 4 - 8 times: The power consumption per bit is less than 5 pJ/b, while a 112 Gbps long - distance electrical I/O consumes 6 - 10 pJ/b of energy, and pluggable optical devices consume about 15 pJ/b.

Latency reduced to 1/10: The latency of TeraPHY is 5 nanoseconds per chiplet + TOF, without forward error correction. The distributed computing systems of high - performance computing and AI cannot tolerate the additional latency of dozens of nanoseconds caused by forward error correction in traditional electrical I/O.

More importantly, the optical I/O solution follows open standards such as UCIe, CXL, and CW - WDM MSA and is optimized for AI training and inference. Its powerful ecosystem enables it to be smoothly integrated into AI systems on a large scale, thereby improving the performance and efficiency of generative AI applications.

Analysis of Technological Advancement:

Dual Breakthroughs in Micro - Ring Modulators and Open Standards

The technological advancement of Ayar Labs is mainly reflected in two dimensions: innovation in underlying devices and openness of the system architecture.

In the field of silicon photonics, the modulator is the core device for converting electrical signals into optical signals. In pluggable optical devices, the mainstream solution is the Mach - Zehnder modulator. Although this modulator is mature and reliable, it is relatively large in size - for CPO (Co - Packaged Optics) applications that need to integrate dozens of optical fibers into a small space for coupling with GPUs, this is a fatal flaw.

The micro - ring modulator used by Ayar Labs is a much smaller device, which is crucial for reducing the size of CPO chips. The working principle of the micro - ring modulator is to use a micro - ring waveguide. When an external electric field is applied, the refractive index of the ring changes, thereby changing the resonant wavelength and achieving the modulation of optical signals. This structure is compact and highly integrated, making it very suitable for high - density optical interconnection applications.

However, the micro - ring modulator has long faced a problem: temperature sensitivity. Since the refractive index of silicon is very sensitive to temperature changes, the resonant wavelength of the micro - ring resonator will drift with temperature, resulting in a decrease or even failure of modulation efficiency. This is also an important reason why many silicon - photonics solutions have been slow to be commercialized.

Ayar Labs' breakthrough lies in the realization of accurate output of optical signals at specific wavelengths in the temperature range of 15 - 100°C through innovative thermal - management design and active wavelength - control technology. This means that TeraPHY can work stably in a wide temperature range in the data center without a complex temperature - control system, greatly reducing system complexity and cost.

Clint Schow, a professor of electrical engineering at the University of California, Santa Barbara, commented: "Integrating optical components into chip packages has always been a dream, and the breakthrough in the temperature stability of the micro - ring modulator is a key step in making this dream a reality."

It is worth noting that, unlike many silicon - photonics companies that choose proprietary protocols, Ayar Labs has adhered to the open - standard route from the beginning. TeraPHY supports mainstream interconnection protocols such as UCIe (Universal Chiplet Interconnect Express), CXL (Compute Express Link), and PCIe, and SuperNova complies with the CW - WDM MSA (Coarse Wavelength Division Multiplexing Multi - Source Agreement) specification.

Behind this strategic choice is a deep understanding of the laws of the industrial ecosystem. For silicon - photonics technology to be truly popularized, chip manufacturers must be able to integrate optical interconnection into existing products with minimal design changes. If proprietary protocols are used, each customer needs to redesign the PHY layer, which will undoubtedly significantly delay the commercialization process.

The adoption of UCIe is particularly crucial. This is a small - chip interconnection standard jointly formulated by industry giants such as Intel, AMD, ARM, Google, Meta, Microsoft, Samsung, and TSMC. By supporting UCIe, TeraPHY can be seamlessly integrated with any chip that supports UCIe, just like