Automotive chip giant launches all-out counterattack

At the time point of 2026, there is a subtle shift in the focus of discussions surrounding automotive chips. As the era of software-defined vehicles enters the engineering implementation phase, the vehicle's electronic and electrical architecture is continuously evolving from a distributed to a centralized and domain-controlled structure. The requirements for computing, real-time control, and system safety within the vehicle are being re-evaluated under the same technical framework.

Against this backdrop, some established chip giants with long - standing expertise in the automotive control field are beginning to showcase their new technological directions. They are no longer confined to the traditional positioning of MCUs. Instead, by introducing more advanced manufacturing processes, higher system integration levels, and design concepts oriented towards software architecture, they are attempting to cover more complex vehicle control and collaborative computing scenarios.

Therefore, at CES 2026, we can see that established automotive chip giants such as NXP, Renesas, and TI are re - entering the competition for the core architecture of software-defined vehicles, centered around system - level capabilities. While manufacturers like NVIDIA and Qualcomm are constantly iterating and updating their intelligent driving and cockpit chips, these established players have launched a new offensive in unison.

From Distributed Dominance to the Impact of Intelligence

In the era of traditional automotive electronics, vehicles adopted a highly distributed ECU architecture. A high - end vehicle was often assembled from dozens or even hundreds of ECUs. Each chip served a specific and stable function - engine control, body electronics, braking systems, steering assistance - each with its own responsibility and without interference. This architecture worked well in the mechanically - dominated automotive industry. Although the complex wiring harness layout brought cost and weight burdens, it was the most reliable solution under the technological conditions at that time.

Under this system, manufacturers such as TI, NXP, ST, Renesas, and Infineon, through their long - term focus on niche areas such as motor control, body control, ADAS front - end, and gateways, gradually perfected the "functional chips" and became the de facto standards in their respective fields. Their core advantages - real - time performance, reliability, low power consumption, and adaptability to harsh environments - were irreplaceable in the mechanically - dominated automotive industry. These established giants not only mastered the core thresholds of automotive - grade certification but also established decades - long in - depth cooperative relationships with vehicle manufacturers and Tier 1 suppliers. Take the Audi Q7 as an example. The vehicle uses 38 MCUs from 7 suppliers. The power domain uses Infineon MCUs, while the chassis and safety domains use chips from multiple manufacturers such as Renesas, NXP, Microchip, and TI.

In that era, a traditional fuel - powered vehicle required approximately 70 MCU chips, while a new energy vehicle needed 100 - 200. Each ECU ran an independent microcontroller responsible for a specific function. The pattern of the MCU market was clear and stable: in 2020, the automotive MCU market reached a scale of $6 billion, accounting for 40% of the global MCU market share. This was a world dominated by traditional automotive electronics manufacturers.

However, the wave of automotive intelligence has completely disrupted this balance.

As the demand for computing power became centralized and the complexity of software increased sharply, the cockpit and intelligent driving functions first exceeded the boundaries of traditional ECUs. Computing - oriented manufacturers such as Qualcomm and NVIDIA entered the market with stronger general - purpose computing power, more mature software ecosystems, and more flexible development toolchains, directly capturing a portion of the core value originally dominated by traditional automotive - grade chip manufacturers.

The rise of Qualcomm is the most representative. Since the launch of the first - generation cockpit chip 602A in 2014, Qualcomm, leveraging its experience in the mobile phone chip field, quickly occupied the cockpit chip market through strategies such as capability transfer and product reuse. The Snapdragon SA8155P, launched in 2019, was the world's first automotive chip with a manufacturing process below 7nm and almost dominated the entire intelligent cockpit market. By the 5nm - process Snapdragon SA8295P launched in 2021, the NPU computing power reached 30 TOPS, nearly 8 times that of the 8155. Data from 2024 shows that in the Chinese passenger vehicle cockpit chip market, Qualcomm's installation volume share is approximately 67%, ranking first in terms of market share. Almost all mainstream vehicle manufacturers, from XPeng, NIO, and Li Auto to BYD, Great Wall, and Geely, have adopted Qualcomm's cockpit chips.

NVIDIA has established stronger dominance in the field of intelligent driving. Since entering the automotive SoC field in 2015, NVIDIA has released a vehicle - grade chip almost every two years, continuously increasing the computing power level. The Xavier chip in 2020 had a computing power of 30 TOPS, and the Orin in 2022 reached 254 TOPS. The current mainstream commercial solution is the dual - Orin - X configuration, with a computing power of 508 TOPS. The new - generation Thor chip launched at the GTC conference in the fall of 2022 has a computing power of up to 2000 TFLOPS, nearly 20 times that of the Orin. Leading vehicle manufacturers such as Li Auto, NIO, XPeng, BYD, and Zeekr are all NVIDIA's customers. NVIDIA expects its automotive business to reach $5 billion in fiscal year 2026.

The intelligent cockpit is no longer just about displaying instruments and playing music. It needs to run complex Android systems, support multi - screen interaction, and voice recognition. Autonomous driving is no longer satisfied with L2 - level auxiliary functions and requires large - scale computing power to integrate perception, high - precision maps, and decision - making planning. Traditional MCUs are facing severe challenges: the complex wiring harness layout, inefficient communication between ECUs, fragmented software development, and high maintenance costs, which were once acceptable, have become heavy burdens in the era of software - defined vehicles.

In this transformation, traditional MCU manufacturers were once in a passive position. Their products are still important in the new architecture, but they are no longer sufficient. More seriously, Qualcomm and NVIDIA not only dominate the high - computing - power chip market but are also continuously penetrating downwards. In October 2024, Qualcomm launched the Snapdragon Cockpit Premier Edition and the Snapdragon Ride Premier Edition platforms, adopting the self - developed Oryon CPU architecture. The performance has increased by 3 times compared with the previous generation, and the AI performance has increased by 12 times. It can support both cockpit and intelligent driving functions on a single SoC, achieving true cockpit - driving integration. NVIDIA's Thor chip also supports multi - domain computing and can efficiently integrate intelligent cockpit and intelligent driving functions on a single SoC.

Strategic Counterattack under the Consensus of SDV

However, when SDV (Software - Defined Vehicle) becomes the industry consensus for the next stage, these established giants have not chosen to withdraw.

As Bosch's proposed domain - control architecture divides vehicle functions into five major areas and the ultimately - targeted central - centralized architecture is gradually implemented, the vehicle's electronic and electrical architecture is undergoing a fundamental reconstruction. According to the prediction of Gasgoo Research Institute, the shipment volume of autonomous driving domain controllers will exceed 4 million units, and the shipment volume of intelligent cockpit domain controllers will exceed 5 million units in 2025, with a compound growth rate expected to be over 50%. The requirements for computing, real - time control, and system safety within the vehicle are being re - evaluated under the same technical framework. Regional controllers need faster processing speeds, connect more devices, and support emerging functions such as edge artificial intelligence.

Facing this trend, established manufacturers such as NXP, Renesas, and TI have launched a new round of offensive in unison. They are no longer confined to the traditional positioning of MCUs. Instead, by introducing more advanced manufacturing processes, higher system integration levels, and design concepts oriented towards software architecture, they are trying to regain control of the automotive core in the new centralized, domain - controlled, and even central - computing architectures.

The logic of this counterattack is clear and firm: although Qualcomm and NVIDIA have advantages in the cockpit and intelligent driving fields, their strengths lie in high - computing - power functions such as perception and decision - making. The vehicle's core control systems - body electronics, chassis control, power management, energy distribution, real - time safety, etc. - still require extremely high real - time performance, reliability, and functional safety levels. These are exactly the areas where traditional MCU manufacturers are most proficient and have the highest moats.

At CES 2026, the signals of this counterattack became particularly clear:

NXP launched the S32N7 super - integrated processor series based on the 5nm process, focusing on body electronics, chassis control, energy management, gateway functions, and L2 - level ADAS. Through hardware - enforced isolation, high - performance interconnection, and distributed AI inference capabilities, it aims to become the system - level coordinator for the vehicle's core functions;

Renesas introduced the industry's first multi - domain automotive SoC R - Car Gen 5 X5H using the 3nm process, integrating 32 Arm Cortex - A720AE cores and 400 TOPS of AI computing power, supporting multi - domain fusion;

Texas Instruments launched the TDA5 series, using the 5nm process, with a maximum computing power of 1200 TOPS, but emphasizing the industry's best energy - efficiency ratio of 24 TOPS/W.

The common feature of these products is that they no longer compete head - on with Qualcomm and NVIDIA in the high - computing - power perception and decision - making fields but occupy the irreplaceable core control positions in the SDV architecture. Through ultra - high integration, support for mixed - criticality systems, hardware isolation and software - defined partitioning, and always - on low - power AI, they provide vehicle manufacturers with a more practical, controllable, and cost - effective intelligentization path.

NXP S32N7: The "Nerve Center" Controlling the Vehicle Core

On January 5th, NXP officially launched the S32N7 super - integrated processor series at CES 2026. This series of processors does not compete in the infotainment or high - end autonomous driving markets but focuses on becoming the system - level coordinator for the vehicle's core functions. The S32N7 targets basic vehicle subsystems such as body electronics, motion and chassis control, energy management, gateway functions, and L2 - level ADAS, positioning itself between high - performance ADAS/IVI computers and distributed actuators.

It is understood that the S32N7 is manufactured based on the 5nm process and includes 32 compatible models, providing functions such as high - performance networking, hardware isolation technology, artificial intelligence, and data acceleration on the system - on - chip. Its core technological advantages are reflected in three aspects:

Hardware - enforced isolation and software - defined partitioning. The S32N7 implements hardware - enforced, software - defined partitioning. Engineers can decide which part of the chip is allocated to which function. These partitions are defined in software but enforced by hardware. Each partition can be independently started, updated, and managed. The isolation measures cover computing cores, memory areas, I/O, and network resources. The fault - isolation logic ensures that faults are limited to the affected functions. This design allows up to eight traditionally independent vehicle domains to be integrated into a single processor while maintaining the non - interference required for mixed - criticality systems.

High - performance interconnection and network integration. The S32N7 integrates vehicle networking functions directly into the SoC, supporting CAN, LIN, FlexRay, and time - sensitive network Ethernet. More importantly, it supports secure, restricted, high - performance PCIe - based interconnection, enabling the S32N7 to exchange data with external ADAS or infotainment computing nodes without exposing unrestricted shared memory. This interconnection allows the system to share sensor data, Ethernet ports, or AI extensions between SoCs with clear access control, supporting modular system expansion while maintaining security and reliability boundaries.

Distributed AI inference capabilities. Different from autonomous driving SoCs that prioritize peak TOPS for perception workloads, NXP has optimized the S32N7 for multiple concurrent AI tasks distributed across the vehicle. The integrated NPU is designed to run multiple medium - scale inference models in parallel, including use cases such as predictive maintenance and vehicle state perception. Since the S32N7 remains active in all vehicle power modes, AI functions can operate normally even when high - power ADAS or IVI processors are turned off. Local inference reduces latency and dependence on cloud connectivity.

Robert Moran, Vice President of Automotive Processors at NXP Semiconductors, said: "Our new S32N7 processor series redefines mobility. Its innovation goes far beyond infotainment and autonomous driving and delves into the vehicle's core functions. For automobile manufacturers, this means simplified processes and significant cost savings. For drivers, this means an extremely intuitive experience, where the vehicle can anticipate their every need."

Currently, Bosch has taken the lead in deploying the S32N7 in its vehicle integration platform. The two parties have cooperated to develop reference designs, security frameworks, and integration tools, significantly shortening the development time.

Judging from various parameters and the targeted market, the S32N7 is not designed for a single generation of vehicles but reserves space for the long - term evolution of SDV. Hardware - enforced isolation, independent updates, controlled interconnection, and always - on AI make it naturally suitable for the requirements of OTA continuous iteration, function - on - demand unlocking, and cross - domain software reuse.

Renesas R - Car Gen 5 X5H: Leading Multi - Domain Fusion with 3nm Process

On December 16th last year, Renesas introduced the R - Car Gen 5 X5H, a high - performance multi - domain automotive SoC in Renesas' fifth - generation R - Car series and the industry's first multi - domain automotive SoC manufactured using the advanced 3nm process. At CES 2026, Renesas' demonstration for the first time showed the various functions of the R - Car X5H. This chip centralizes multiple vehicle functions on a single computing node while supporting ADAS, infotainment systems (IVI), and gateway functions.

It is understood that the processor part of the R - Car Gen 5 X5H includes 32 Arm Cortex - A720AE cores for high - performance application computing and 6 Cortex - R52 lock - step cores to provide real - time control and functional safety (ASIL D) support. An AI accelerator is also integrated on the chip, providing a maximum computing power of 400 TOPS and supporting further performance improvement through chiplet expansion. The GPU performance is approximately 4 TFLOPS, used for cockpit display and graphics processing.

Notably, the R - Car X5H supports multi - domain fusion, capable of simultaneously processing inputs from 8 high - resolution cameras and outputting to 8 8K2K displays. The chip platform provides a unified development environment, including Linux, Android, XEN virtualization, and a supporting Whitebox software development kit, which can be integrated with multiple operating systems (AUTOSAR, QNX, SafeRTOS, etc.) and third - party software stacks to accelerate the development of vehicle software.

Vivek Bhan, Senior Vice President and General Manager of High - Performance Computing at Renesas Electronics, said: "Since the launch of our most advanced R - Car device last year, we have been committed to developing market - oriented solutions, including delivering chip samples to customers earlier this year. We are working hand in hand with OEMs, Tier 1 suppliers, and partners to quickly launch a complete development system to power the next - generation software - defined vehicles. These intelligent computing platforms can provide a smarter, safer, and more connected driving experience and can be expanded according to future artificial - intelligence mobility needs."

Compared with the series of advanced parameters brought by the 3nm process, the platform - oriented intention of the R - Car Gen 5 is more worthy of attention. The unified CPU architecture, cross - generation software compatibility, scalable AI acceleration, and support for mixed criticality make it more like a continuously evolving computing base rather than a one - time performance product.

Texas Instruments TDA5: A 1200 TOPS Computing - Power Chip with Energy Efficiency as the King

At CES 2026, Texas Instruments also launched the TDA5 series of cross - domain fusion SoCs supporting L3. This series of processors is built using the 5nm process, providing a maximum AI computing power of 1200 TOPS. More importantly, this chip can support 24 TOPS of computing power per watt of power consumption. The person in charge of the processor product organization department at Texas Instruments emphasized: "For electric vehicles, the single - charge driving range is a key indicator, so chips with lower power consumption and higher performance are needed. The TDA5 has the industry's best energy efficiency."

The technological innovation of the TDA5 is concentrated in three aspects. First, the integration of the neural processing unit C7. Texas Instruments has achieved 12 times higher AI computing performance than the previous - generation product while maintaining similar power consumption. Second, it supports chipset design. The TDA5 is built based on the UCIe open - standard interface. This technology splits high - performance semiconductor functions into multiple parts and then combines them, thus being able to provide customized applications for customers.

Texas Instruments believes that compared with SoCs mainly based on a single type of operation unit, SoCs using multiple operation units have higher energy efficiency and can improve performance in the central computing ECU. An SoC with multiple operation units can simplify the development, deployment, and execution of advanced autonomous driving function software because it can offload specific tasks to dedicated IP modules, including high - performance NPUs and vision processors supported by dedicated built - in memories.

It is reported that the TDA5 SoC includes multiple dedicated subsystems, each carefully designed to meet