Dialogue with Dr. PANG Linyong, an expert in semiconductor lithography: Full-chip ILT is a key technology for the downward iteration of semiconductors

In the field of semiconductor manufacturing, lithography technology is a key process for realizing the pattern transfer of integrated circuits. With the continuous advancement of Moore's Law, the feature size of chip patterns is constantly shrinking, and lithography technology is facing unprecedented challenges. Among them, the optical proximity effect causes deviations between the lithographic patterns on the wafer and the mask design patterns. This makes it an indispensable key step to correct the mask based on computational lithography technology (OPC) to weaken the influence of the optical proximity effect. As one of the core technologies of modern lithography processes, computational lithography has evolved from early rule - oriented to model - driven and has flourished in the past nearly 20 years, becoming a key step in mask pattern processing. However, as the process nodes evolve towards more advanced technologies, traditional methods are limited by rule constraints and insufficient optimization freedom, and gradually struggle to meet the manufacturing requirements of more complex chip designs. Against this background, Inverse Lithography Technology (ILT) has emerged with its unique optimization concept, providing a new solution for the lithography process of advanced processes.

D2S, Inc, as a leading enterprise in the field of GPU - accelerated solutions for semiconductor manufacturing, relies on its technological accumulation in natural simulation, image processing, and deep learning to provide innovative model - based processing technologies for the manufacturing of nanoscale devices. It is also the main sponsor of the eBeam Initiative and a founding member of the Center for Deep Learning in Electronics Manufacturing (CDLe). During the 9th International Workshop on Advanced Patterning Science and Technology (IWAPS 2025), Dr. Leo Pang, the Chief Product Officer of D2S, Inc in Silicon Valley and an expert in semiconductor lithography, was interviewed by ICViews on topics related to computational lithography and ILT technology.

As the founder of ILT in the industry and the initiator of this term, Dr. Pang holds 38 patents, with 30 more pending. He has published 90 papers in international journals and conferences. He is an expert committee member of the International Society for Optics and Photonics (SPIE), the chairman of the Lithography Sub - conference of the CSTIC China International Semiconductor Conference, the editor of the SPIE lithography journal JM3, and the chief editor of the deep - learning special issue.

Computational Lithography and Inverse Lithography Technology (ILT) Drive the Continued Development of Advanced Processes

During the evolution of chip processes towards the 2nm and more advanced nodes, the complexity of the lithography process not only increases exponentially but also requires the adoption of EUV lithography technology. As the core part of semiconductor manufacturing, computational lithography corrects and verifies the mask patterns before lithography through software simulation and algorithm optimization, avoiding process defects in advance and ensuring that the chip patterns can be accurately "replicated" onto the wafer. It is a key bridge connecting chip design and manufacturing, directly determining the feasibility and yield of advanced processes.

All EUV masks are written by Multi - Beam devices. The main equipment manufacturers are IMS and NuFlare. NuFlare's latest multi - beam mask writers, MBM–2000, MB - 3000, and the next - generation MBM - 4000, all have pixel - level dose correction (PLDC) function. And PLDC is one of D2S's most breakthrough innovations. Different from traditional optical proximity correction (OPC) and mask process correction (MPC) tools that operate at the polygon level, PLDC works directly at the pixel level. PLDC achieves all MPC functions by accurately calculating the exposure dose required for each pixel in the multi - beam mask writing device, ensuring the highest degree of coincidence between the actually manufactured mask patterns and the target patterns output by OPC/ILT. Dr. Pang said, "From this perspective, we ensure the further development of EUV. From the perspective of ILT, at Low NA, ILT is not really needed, but at High NA, people think ILT is necessary."

Inverse Lithography Technology (ILT) actually reverses the entire lithography process: according to the pattern to be exposed on the wafer, by solving the inverse problem mathematically, the required pattern on the photomask is found. It is known as the ultimate technology of OPC and RET and has been adopted by major manufacturers as one of the core lithography technologies. Compared with traditional optical proximity correction (OPC) technology, ILT can more accurately compensate for complex factors such as optical distortion and etching effects of the lithography system by reversely deriving the physical laws of the lithography process, generating better mask patterns. In advanced processes, the importance of ILT is also reflected in accuracy improvement and full - chip adaptation. As the chip line width continues to shrink (for example, the line width at the 2nm node is approaching the physical limit), traditional OPC has difficulty considering subtle physical processes such as etching effects, while ILT can incorporate these effects into the model, significantly improving the accuracy of pattern transfer and reducing device performance deviations. On the other hand, the patterns of advanced - process chips are extremely complex, and "hotspots" (areas prone to process defects) are spread throughout the entire chip. Correction technologies targeting only local hotspots can no longer meet the requirements, and full - chip ILT has become the only way to solve this problem.

GPU Acceleration Brings Inverse Lithography Technology (ILT) to the "ChatGPT Moment"

Although ILT technology is crucial for advanced processes, before the application of GPU acceleration technology, the development of ILT was long limited by the efficiency bottleneck. Just as the AI field had difficulty breaking through large - scale model training before the popularization of GPUs, full - chip ILT was once in a dilemma of "theoretically feasible but impossible to implement in engineering".

Before the intervention of GPU technology, ILT mainly relied on CPUs for calculation. However, the serial computing architecture of CPUs was difficult to handle the massive data and complex algorithms of full - chip ILT. First, the computing efficiency was extremely low: Full - chip ILT involves parallel computing of hundreds of millions or even billions of pixels. CPUs need to process data point by point, and it may take weeks to complete a single full - chip ILT correction, which cannot meet the mass - production cycle requirements of semiconductor manufacturing at all. Second, the functional limitations were significant: Due to the insufficient computing power of CPUs, traditional ILT could not only achieve full - chip processing but also had difficulty incorporating key physical models such as etching effects. Dr. Leo Pang mentioned, "Calculating the etching effect with a CPU requires associating open spaces, and the process is very slow, so no one in OPC does the etching model." This led to the inability to fully exert the accuracy advantage of ILT. Finally, the practicality was insufficient: Previously, the industry could only use CPUs to process local "hotspot areas" of ILT (such as the Luminescent company where Dr. Leo Pang once worked). However, hotspots are spread throughout advanced - process chips, and local correction cannot solve the fundamental problem, so ILT technology has never been implemented on a large scale.

The parallel computing architecture of GPUs precisely solves the efficiency pain point of ILT. Just as GPUs have promoted AI into the "ChatGPT moment", GPUs have also enabled ILT to achieve a qualitative change from "local correction" to "full - chip application", becoming an enabler for the implementation of ILT technology.

The practice of Dr. Leo Pang's team fully verifies the important value of GPU acceleration. First, full - chip ILT has become a reality. GPUs perform parallel computing in units of pixels and can process hundreds of millions of pixel data simultaneously, completely breaking the efficiency bottleneck of CPU serial computing. "Without GPUs, you can't achieve Full - Chip ILT," Dr. Leo Pang emphasized. "Calculating full - chip ILT with a CPU takes too long and has no engineering value at all." The super - large virtual CPU - GPU invented by D2S solves the biggest problem of stitching errors in full - chip ILT, making full - chip ILT truly applicable to mass production. Second, both accuracy and efficiency are improved. GPUs not only improve the computing speed but also enable the rapid calculation of physical effects (such as etching effects) that could not be incorporated before. D2S has found a fast - calculation method for the etching effect through GPU - optimized algorithms. What the CPU could not calculate before, the GPU can now calculate quickly, making ILT not only faster but also more accurate. Finally, it can be extended to mask correction. GPU acceleration has also been applied by D2S in the field of mask correction, developing pixel - level dose correction (PLDC) technology. For traditional mask process correction (MPC), especially curvilinear mask correction, customers reported that "it takes several weeks to complete". D2S uses GPUs to complete the correction synchronously during the pixel conversion process. Multi - beam mask writing requires rasterizing polygons into pixels first. D2S directly adds a correction algorithm at this step, "without increasing the writing time of the mask direct - writing device and breaking through the original limitations", achieving "zero turn - around - time" for mask correction.

It is worth noting that inspired by D2S's use of GPU - accelerated ILT, NVIDIA also recognized the importance of GPU acceleration in computational lithography and launched the cuLitho library based on GPU - accelerated computational lithography, hoping to benefit companies doing OPC. Currently, it has received positive responses from TSMC and Synopsys.

AI Drives the Development of Computational Lithography

According to the statistics and forecasts of QYResearch, the global sales of computational lithography software reached $1.268 billion in 2024 and are expected to reach $2.368 billion in 2031. AI - enhanced solutions are beginning to be widely used, and AI technology is becoming the "new engine" in the field of computational lithography, injecting new impetus into the iteration of core technologies such as ILT. Dr. Leo Pang believes that the core changes brought by AI to computational lithography are mainly reflected in two major directions: "model construction" and "ILT acceleration", and it forms a synergistic and complementary relationship with existing technologies rather than a substitution relationship. First, in terms of model construction optimization: In computational lithography, the mechanisms of some physical effects (such as Negative Tone Development, NTD) are complex, and traditional mathematical models have difficulty accurately describing them, resulting in insufficient simulation accuracy. AI technology can learn the laws of effects from a large amount of experimental data or rigorous simulation through a data - driven approach and quickly build high - precision models. "It was difficult to build models in the traditional way before, but now we can use AI to build models, and many companies are already doing this, including us," Dr. Leo Pang said. In addition, in terms of ILT acceleration, although GPUs have significantly improved the efficiency of ILT, the computing volume of full - chip ILT continues to increase with the advancement of the process. AI (especially deep learning) can further accelerate the ILT process. By using deep - learning models to learn the "high - quality data" generated by high - precision ILT, approximate optimal correction results can be quickly output later. However, Dr. Leo Pang emphasized, "Even if we want to use deep learning to accelerate ILT, we still need the original ILT because deep learning needs to learn from data, and this data needs to be generated by ILT." This means that the role of AI is to "amplify the advantages of ILT" rather than replace ILT.

Full - Chip ILT Will Empower the "Long - Term Iteration" of Semiconductors

When talking about the future of computational lithography, Dr. Leo Pang believes that full - chip ILT will become a key technology to "empower the entire semiconductor industry to go much further". Currently, D2S's core products (such as full - chip ILT and PLDC) are all centered around promoting full - chip curvilinear ILT and curvilinear mask technology. Once the technology matures, it will bring a "freedom revolution" to chip design: The design end can use curvilinear patterns to optimize the chip structure, reduce the number of layers, and lower power consumption. IMEC (Interuniversity Microelectronics Centre) also pointed out in a recent paper that "if curvilinear patterns can be used in design, it may enable three generations of semiconductor technology". This means that full - chip ILT is not only a necessary technology for the current 2nm process but also will become the "basic platform" for the iteration of multiple generations of semiconductor technologies in the future. The continuous empowerment of GPUs and AI will make this technology a reality faster. Due to the maturity of the technology, full - chip ILT has more extensive applications in DUV, which can help expand the process window, improve the yield, or achieve smaller nodes without changing the lithography machine.

This article is from the WeChat official account “ICViews” (ID: ICViews), author: Pengcheng. It is published by 36Kr with authorization.