Comprehensive Overview of Popular Chips: Recap of Hot Chips 2025 First Day

Hotchips 2025: Intel's 288-core Processor, AMD RDNA4, IBM Power11, and RISC-V Release

The annual Hotchips event officially kicks off. Leading manufacturers from around the world shared their views and designs on chips at the conference. In this comprehensive article, we will share the leading CPU designs from Intel, IBM, and emerging RISC-V upstarts, as well as the designs from GPU giants such as NVIDIA.

The full text of the article is as follows:

A High-Performance RISC-V Design

Condor Computing, a subsidiary of Andes Technology, focuses on developing high-performance RISC-V cores. Cuzco is their first design, completed by a relatively small team of only 50 engineers.

Currently, several companies are developing high-performance RISC-V cores. Condor aims to be a leader in the industry, offering the highest performance within a similar power consumption range. The RISC-V ecosystem is still maturing, so we are currently in a development stage where there is room for a large number of participants, but eventually, there will be a knockout competition, leaving only a few players.

At a very high level, Cuzco's design is very similar to other high-performance processors. This means it has a wide front end, a fairly deep 256-entry reorder buffer, 8 execution pipelines, and so on. Condor doesn't intend to reinvent the wheel; their goal is to build a more optimized wheel than other players in the RISC-V ecosystem.

Cuzco is a complete IP design. That is, it's not just a CPU core but also has cache and coherence management functions; it can basically be connected to the memory and I/O buses. But undoubtedly, the CPU core is the highlight of this design - and this is also what Condor focuses on the most.

Cuzco complies with the RISC-V RVA23 specification, the first major specification for high-performance RISC-V computing. Notably, this specification includes support for vector instructions, which is crucial for high-performance computing - not to mention processing large amounts of data in an energy-efficient manner.

Condor adopted a time-based microarchitecture for Cuzco. This architecture will soon become very advanced and cannot be fully explained in a live blog, but essentially, they use hardware compilation for instruction scheduling. In short, they try to improve out-of-order execution by designing a method that requires fewer transistors and is thus more energy-efficient. In some ways, this sounds like a variation of the traditional method of pre-static instruction scheduling in software (through the compiler), but part of the work is transferred to the hardware, without completely abandoning the idea.

Ultimately, Condor believes their hardware scheduling system can achieve better results with lower power consumption and complexity than traditional OoO scheduling. Since power consumption is a key bottleneck for overall performance, the optimization here will bring higher performance.

Cuzco adopts a slice-based CPU design with a maximum of 8 CPU cores in total.

Compared with other OoO designs of the parent company, the Cuzco team believes their design has almost twice the performance per clock in SPECint2006 compared to Andres' current AX65 core.

The IP itself will be delivered with a maximum of 8 cores, having a private L2 and a shared L3. It is connected through a wide CHI bus.

The Quirky Japanese CPU

Today's second-ranked CPU in the Hot Chip 2025 special is Pezy Computing, a quirky Japanese CPU development company specializing in multi-instruction multi-data (MIMD) CPU design.

MIMD is an old concept in CPU design, but we don't often see it in the real world. Most designs are variants of single-instruction multi-data (SIMD). However, MIMD has the potential to outperform SIMD in performance because it can handle scenarios with highly independent/divergent threads more gracefully, where only a few (if any) threads use the same instruction simultaneously.