Why are they all targeting the 12nm process?

12 nanometers, a process node that was already in mass production a decade ago, why has it become the focus of the current chip industry? In the past six months, from many domestic chip manufacturers such as Unisoc, Loongson, ASR Microelectronics, Fudan Microelectronics, Jiangyuan Technology, Transcend, Guoxin Technology, Yaoyushi Core, to international giants such as Sony, Intel, and UMC, they have all unexpectedly set their sights on the 12nm process node.

Image source: TSMC

This is a systematic re - evaluation driven by the marginalization of computing power, cost sensitivity, industrial geopolitics, and packaging systematization. In the face of advanced processes with high costs and low production capacity, 12nm is being redefined as the "golden mid - node", and its commercial value and strategic significance are rising rapidly.

The application spectrum of 12nm is expanding rapidly

Let's first take a look at some recent typical domestic products using 12nm process technology:

In June, Unisoc released the 4G flagship wearable platform W527, which uses a 12nm process, has a built - in 1 + 3 core heterogeneous architecture and dual ISP, and supports 16 + 8 dual cameras;

(Image source: Unisoc official website)

Loongson 3C6000 uses the domestic 12nm process. It realizes 16 - core/32 - thread computing through instruction set and interconnection architecture optimization and supports a maximum of 256 logical cores in parallel. It achieves technical benchmarking against Intel's 7nm Xeon without relying on advanced processes;

(Image source: Loongson Technology official website)

Fudan Microelectronics released the smart glasses chip MC6350 at CES 2024. The 12nm process supports a smaller chip size (8*8mm), ultra - low power consumption (the power consumption of video shooting in typical scenarios is only 1/4 of the market's mainstream smart glasses chips), and AI ISP image optimization;

On July 9th, Pinggao Co., Ltd. and Jiangyuan Technology jointly released the Pinyuan AI all - in - one machine. The series of "Pinyuan AI all - in - one machine" products equipped with Jiangyuan's D10 accelerator card use a 12 - nanometer process. The entire process from design, manufacturing to packaging relies on the local industrial chain, achieving full - process autonomy of high - computing - power AI chips;

Yaoyushi Core, an XR spatial computing chip manufacturer that just completed tens of millions of yuan in Series A financing in November 2024, will improve semiconductor performance with its second - generation XR chip. It uses a 12nm process, further reducing power consumption while maintaining cost advantages;

ASR1901 of ASR Microelectronics is a 5G industrial Internet of Things platform based on the R16 protocol. The 12nm process helps it achieve low latency and high energy efficiency;

Transcend ETD410T eSSD: Equipped with a controller chip based on a 12nm process, it improves efficiency and stability in the embedded storage market;

Suzhou Guoxin Technology × M31: In January 2025, M31 Technology (hereinafter referred to as "M31") and Suzhou Guoxin joined hands for the first time to enter the advanced process field. Guoxin Technology commissioned M31 to customize a GPIO IP based on a 12 - nanometer process. This IP supports an operating frequency of 125MHz and multi - voltage operation, and is used in automotive noise reduction DSP chips (benchmarking against ADI ADSP21565). It has been successfully introduced into the pre - research of many domestic automobile manufacturers.

Sony revealed in an interview in June that the logic circuit of future sensors will use a 12 - nanometer process.

This batch of products spans multiple major segmented markets such as AI wearables, edge servers, automotive electronics, consumer Internet of Things, eSSD controllers, XR visual processors, and image sensors, indicating that the application spectrum of 12nm is developing towards "wide coverage, multiple scenarios, and high practicality".

Why 12nm? Four logics revitalize the old node

Although 12nm is between "advanced" and "mature" in the technology spectrum, it is the most advanced process node using non - EUV lithography technology, showing obvious cost advantages. Its commercial value is recovering, and four logics are revitalizing this old node:

1. Currently, global AI applications are expanding from "central large models" to "edge inference". Edge devices such as XR, wearables, IoT, and automotive chips are sensitive to power consumption, area, and cost. Although 7nm/5nm is powerful, it is expensive and difficult to produce; although 28nm/40nm is cheap, its performance is insufficient. 12nm just hits the balance point of "performance - power consumption - cost", becoming an ideal choice for edge AI SoCs.

2. It can be seen that many domestic chip companies have chosen this node, which is also largely a re - evaluation of the "safe process" under geopolitics. Under the dual pressures of "technology sanctions" and "chip localization", 12nm has become an ideal entry point: 12nm is not at the cutting - edge (not subject to restrictions) and can support modern mainstream mid - to - high - end applications; there is a relatively mature manufacturing foundation in China/Southeast Asia/Middle East (it can be implemented);

3. The "system upgrade" route of mature equipment + advanced packaging. The 12nm node has a high process tolerance highly compatible with advanced packaging (such as 2.5D, 3D - IC) technologies. The current design trend of system - level chips emphasizes "heterogeneous integration", which requires mixing chips of multiple nodes in one package. Using the 12nm process to manufacture logic chips and matching them with bare chips such as AI accelerators/memories can quickly build a "quasi - advanced system" at a much lower cost than the full - process of advanced nodes.

4. The resources of advanced processes are in short supply, and customers are turning to mid - nodes. The global supply and demand of advanced processes (7nm and below) are in short supply, especially limited by EUV production capacity. TSMC and Samsung are heavily focused on high - end customers, and edge customers/vertically segmented customers have no hope of queuing. At the same time, customers of mature nodes (28/40nm) are gradually upgrading, "forcing" the mid - stage process. Therefore, 12nm has become a natural "diversion node" to bear the production capacity pressure from both ends.

From a trend perspective, 12nm is changing from a "transitional node" to a new "strategic node". It may not define the future computing power limit, but it will dominate: the next - generation edge AI terminals, mid - to - high - end intelligent perception systems, most consumer electronics and wearable SoCs, a new round of domestic self - developed IP and EDA tool verification platforms, automotive electronics and XR system chips. 12nm can be said to be the real "finale work" of the non - EUV era.

The importance of foundries on 12nm

From the perspective of foundries, among the three major players (TSMC, Samsung, and Intel), only TSMC has a publicly available and formal 12nm process technology, and GlobalFoundries also has it. However, TSMC has not given much attention to it. TSMC's 12nm FinFET Compact (12FFC) is an optimized version of its 16nm family (16FF / 16FF+ / 16FFC) and went into mass production in 2017.

TSMC successfully trial - produced the 16nm FinFET process technology as early as 2013 and officially produced the industry's first fully functional 16nm FinFET network communication processor in 2014. After that, TSMC further mass - produced the enhanced version of the 16nm FinFET process (16FF+) in July 2015 and the streamlined 16nm process (16FFC) in 2016. The streamlined 12nm process technology (12nm FinFET Compact Technology, 12FFC) further increases the crystal density to the extreme of the 16nm generation and entered production in the second quarter of 2017.

However, industry insiders generally believe that TSMC's 12nm is for competing with Samsung's 8nm. Samsung's 8nm Low Power Plus (8LPP) was put into production in Q4 2018. As an optimized version of the 10nm process, it uses DUV multiple patterning technology. Although the technology names are different, both have not entered the EUV era, and their PPA (power consumption - performance - area) performances are similar, and they form direct competition in multiple product markets. Samsung's 8nm was once considered an option for "low - cost replacement of 7nm", but in reality, its heat control is poor, and the power consumption is not as expected. In addition, many EDA manufacturers (such as Cadence, Synopsys) are also more actively supporting the 12nm platform, with a higher frequency of PDK updates and smoother integration of AI - assisted design. This has also made TSMC's 12nm popular again, especially for terminal products that are more sensitive to power consumption and system packaging.

In TSMC's expansion map around the world in recent years, 12nm also appears frequently. For example, the Kumamoto factory in Japan and the European semiconductor manufacturing company jointly established by Bosch, Infineon, and NXP in Europe all have relevant plans for 12nm.

Moreover, UMC and Intel have also set their sights on this "fat meat". At UMC's annual general meeting of shareholders on May 28th this year, UMC's Chief Financial Officer Liu Qidong said that the 12nm process jointly developed by the company and Intel is one of UMC's most important development plans at present, and it is expected that this project will achieve mass production in 2027.

UMC and Intel announced in early 2024 that they would jointly develop a 12nm process platform to cope with the rapid growth of the mobile communication and network infrastructure markets. At that time, UMC said that UMC and Intel would adopt a division - of - labor cooperation model. Intel would be responsible for local manufacturing, while UMC would focus on process development, sales, and service process technologies.

Why did these two choose to cooperate? And why did they choose 12nm? There are many reasons.

For UMC, which gave up developing processes below 12nm as early as 2018 and focused on mature nodes (such as 28nm, 40nm, etc.), the current shift does not mean embracing "advanced processes" again, but "extending the ceiling of mature processes". Not pursuing the 7nm and 5nm battlefields, but moderately upgrading to 12nm can extend the customer life cycle and meet the upward - going needs of customers.

In recent years, the mature processes in the Chinese mainland have been very competitive, and the field of 28 - nanometer and below processes where UMC once had a sure - win situation is becoming a red ocean. If UMC does not continue to invest in more advanced process technologies, it may lose its competitive advantage. This is actually a move for UMC to "seek progress while maintaining stability": using limited investment to unlock the customer upgrade path and new market blue oceans.

As for Intel, a small 12nm should not be a difficult task. Then why does it still need to cooperate with UMC on 12nm?

First of all, for Intel at present, 18A is the top priority. Almost all of Intel's advanced process resources are bet on winning against TSMC's 2nm;

Secondly, although Intel has a 14nm process, it is mainly designed for its own products. Directly using it for foundry services requires significant modifications to design rules, platform verification, and PDK development. It is more time - and labor - saving to jointly develop 12nm using UMC's existing technology platform;

Moreover, Intel's independent foundry department wants to learn how to build a "T - like" process, and UMC knows very well how to do this. By cooperating with UMC, Intel can learn its practical experience in foundry customer service, PDK management, and platform development processes. It needs to undertake new customers and meet different foundry needs.

The two parties set up production capacity in Intel's Fab plant in Arizona, using production lines 12, 22, and 32 of the wafer factory. This is not only close to customers but also bypasses the risks between China and the United States. At the same time, it also meets the strategic requirements of the US government for domestic wafer production capacity, technology alliances, and supply - chain security. Simply put, Intel needs utilization, and UMC needs production capacity.

According to a report by CommonWealth Magazine, in the past year, not all Taiwanese engineers who went to Arizona were from TSMC. UMC also sent some of its own engineers, and these engineers often appear in Intel's campus in the Phoenix area.

Overall, UMC is not trying to compete in advanced processes but is seizing the opportunity window of customer process upgrades + geopolitical manufacturing. It uses Intel to supplement the manufacturing end and realizes the transformation from "cost - control - oriented" to "mixed - value - oriented". Although UMC publicly claims that its cooperation with Intel is a hedge against the Chinese market, "its deep - seated purpose is to seize market share from TSMC," a source said. Intel is not short of technology but short of time, service experience, and production - capacity flexibility. This cooperation is a "strategic outsourcing" in foundry layout.

Conclusion

In general, 12nm is at the best balance point between technology and business. It is mature and stable enough to provide the power - consumption - to - performance ratio required by the mid - to - high - end market; it is economical enough to meet the diversified application needs of edge AI, IoT, wearables, automotive regulations, etc. It is also a new focus for industrial - chain security and foundry cooperation. For this reason, this "old node" is rising against the trend and has become a strategic weapon for various manufacturers to both defend and attack. In the future, with the in - depth development of advanced packaging (3D IC, hybrid bonding) and chip system - level optimization, 12nm may play a more important "central" role, serving as a bridge from "chip design" to "system solutions".