Why is the US leading in the chip industry?
The United States' leadership in the semiconductor technology field is crucial for its economy and national security.
To win the competition for technological leadership and in key industries enabled by semiconductors, such as artificial intelligence, high - performance computing, advanced communications, quantum technology, energy, defense, medical technology, and transportation, the United States must re - establish its position as the center of semiconductor innovation. Federal research projects established under the National Defense Authorization Act for Fiscal Year 2021 and funded by the CHIPS and Science Act are working to address the ever - changing nature of the industry, its technologies, and most importantly, the way innovation operates. These investments are beginning to fill specific gaps in the United States' semiconductor competitiveness, resilience, and supply - chain security. Moreover, these investments are being made at a critical moment when drastic industry changes are reshaping the innovation landscape.
Key Points
- To win the global competition for technological leadership, the United States must maintain its leading position in semiconductor innovation.
- The CHIPS R & D projects have the potential to implement an aggressive, comprehensive, and industry - aligned strategy that reflects the industry's latest innovation trajectory.
- These projects have made progress in deploying resources to awardees, and multiple projects are currently underway. These projects have begun to develop the necessary infrastructure, with final contracts signed for small - scale sites and large - scale facilities, and contract negotiations are currently in progress. More progress is needed to develop a research agenda that aligns with industry priorities and mass - production needs and to start implementing this agenda.
- As these projects continue to be implemented, they must be maintained at an appropriate level and remain committed to industry - oriented planning.
Increase R & D Investment to Meet the Intensifying Competition for Innovation Leadership
In recent years, governments around the world, whether allies or competitors, have been in fierce competition for advanced semiconductor R & D resources, as they understand that the location of cutting - edge research determines the growth location of the most advanced enterprises. The semiconductor research projects funded by the federal government through the CHIPS Research and Development Office (CRDO) are committed to implementing an ambitious, comprehensive, and industry - coordinated strategy to ensure that the most advanced semiconductor technologies are developed in the United States, manufactured in the United States, and benefit the U.S. economy. The CRDO projects are making access to these innovative assets more democratic, which would otherwise be unavailable without public funding. The CRDO projects reviewed in this article are as follows:
R & D Investment Will Maintain U.S. Manufacturing Leadership in the Long Run
The CHIPS R & D projects are an important supplement to the $540 billion investment in the United States' domestic semiconductor manufacturing capacity. In the past, the product cycle in this industry was two years. However, as the industry transitions to new innovation strategies, the product cycle is accelerating. The United States must win the competition to be the global core of semiconductor innovation to keep these domestic facilities at the forefront in the long term. In addition, the industry - driven nature of the Core R & D Office (CRDO) projects is designed to support the continuous revitalization of the U.S. semiconductor supply chain, which is consistent with the government's priority of enhancing U.S. innovation and manufacturing competitiveness. Moreover, different from traditional government - funded projects aimed at investing in early - stage technologies, the CRDO projects have a unique mission to activate the technologies required for large - scale production in the short term.
The Importance of Semiconductor Research Projects
As these research projects progress, they are expected to address the innovation challenges faced by the semiconductor industry and drive progress across the entire computing stack.
I. Moore's Law and Future Development Trends
In recent years, new ways of semiconductor innovation have emerged, requiring new cooperation and technology - development methods. In the past few decades, the improvement of computing performance has mainly been achieved through "miniaturization" - minimizing the functions on a chip to accommodate more transistors on a single silicon wafer. Therefore, "Moore's Law" predicts that the number of transistors on a chip will double every two years, while the cost will decrease. For decades, this innovation model has achieved remarkable results, and the pace of Moore's Law continues to this day. However, new innovation frontiers bring great hope for a leap in the computing performance of advanced logic, memory, and analog devices. These new methods go beyond Moore's Law and call for a "full - stack" strategy - innovation in software, materials, design, architecture, and packaging - and require collaboration across the entire value chain. Meanwhile, for an increasing number of applications (such as certain end - uses in the industrial, medical device, and automotive fields), performance is no longer solely measured by the number of transistors; instead, new solutions bring new value propositions to new end - markets, such as ultra - low power consumption, high bandwidth, the ability to operate at higher voltages, higher stability at higher temperatures, or lower latency.
II. Federal Investment Boosts Innovation
New customer demands are repositioning and expanding the way the semiconductor industry innovates, and the CHIPS R & D projects aim to provide the necessary infrastructure and collaborative research platforms to ensure that the U.S. semiconductor ecosystem stays ahead of global competitors in all dimensions of innovation.
As a supplement to the federally - supported research projects, these new projects fill the gaps in the U.S. semiconductor ecosystem, allowing fierce industry competitors to jointly address important innovation needs in a pre - competitive collaborative space.
Guided by industry leaders and technology roadmaps, these project frameworks enable the National Advanced Packaging Manufacturing Program (NAPMP), the National Semiconductor Technology Center (NSTC), the SMART USA initiative, and Metrology to have a significant and rapid impact on the nation while ensuring that the United States leads global competitors in future technology races. The total funding for these projects is approximately $11 billion, allocated over five years as follows:
To effectively compete in the global semiconductor innovation race, these projects must be maintained at an appropriate level. Maintaining an appropriate funding level will ensure that these projects have sufficient resources to carry out their work and establish strong connections with industry partners.
III. Overview of CHIPS R & D Projects
Four projects managed by the U.S. Department of Commerce aim to meet the evolving technological development needs of the U.S. semiconductor industry. These projects were developed with full consideration of industry opinions, and continuous industry insights are crucial to ensure that these projects remain closely connected with industry partners. An overview of these projects is as follows. For more detailed information, please refer to the rest of this report.
Innovation through Advanced Packaging Technology
Advanced packaging is a new semiconductor technology that is expected to accelerate the performance improvement of the most powerful chips in the fields of artificial intelligence and high - performance computing (AI and HPC). It will also facilitate the faster and more cost - effective design and manufacturing of customizable systems to meet the needs of high - mix, low - volume markets, such as defense applications that are crucial for national security. In the past, the performance of the most advanced chips was limited by the functions that could be achieved on a single two - dimensional silicon wafer (i.e., "system - on - a - chip", SOC).
Now, advanced packaging technology allows the components of a chip system to be manufactured separately and then integrated into a single package, ultimately increasing the total silicon content of the entire chip (and thus the computing power). Traditional packaging does not directly affect chip performance, while advanced packaging has now become a key means of improving computing performance. In addition, by manufacturing different components of the chip separately, wafer fabs can simplify the manufacturing process, increase factory output and yield, and achieve more sustainable innovation and product improvement, as all components of the system no longer need to be designed and manufactured together, thereby improving profitability.
Although the earliest advanced packaging technologies are now on the commercial market, most of their potential remains untapped - and global leadership in this critical area is still up for grabs. The United States currently faces a severe shortage in the packaging supply chain, with its assembly, testing, and packaging capacity accounting for only 4% of the global total. Given the upcoming rise of advanced packaging's role in driving computing performance, it is an excellent strategic opportunity for the United States to vigorously develop advanced packaging and seize this growing high - value - added area to cultivate domestic capacity.
The U.S. Congress recognized the importance of semiconductor packaging innovation and established the National Advanced Packaging Manufacturing Program (NAPMP), aiming to "strengthen the advanced testing, assembly, and packaging capabilities of semiconductors in the domestic ecosystem" (15 U.S.C. 4656(d)). Led by the National Institute of Standards and Technology (NIST), this program focuses on packaging applications that are crucial for the public interest, namely artificial intelligence (AI) and high - performance computing (HPC). NAPMP is coordinating extensively with other projects (including the Defense Advanced Research Projects Agency (DARPA)'s Next - Generation Microelectronics Manufacturing Program) to invest in the semiconductor and AI ecosystems.
NAPMP's mission is to develop an overall strategy to address these urgent challenges and promote the prosperity of the domestic advanced packaging industry. The NAPMP strategy is built around six identified research areas:
1. Materials and Substrates
2. Equipment, Tools, and Processes
3. Power Delivery and Thermal Management
4. Photonics and Connectors
5. Co - Design, EDA, and
6. Chiplet Ecosystem
Appendix I details the six R & D priority areas and their importance for semiconductor innovation. As of June 2025, NAPMP has finalized $300 million in funding for its first R & D grant project, focusing on the materials and substrates area. In addition, the project has signed an $1.1 billion contract to establish its flagship project, the Advanced Packaging Pilot Facility (APPF). This facility will be co - located and operate in tandem with the National Semiconductor Technology Center (NSTC) pilot facility in Arizona. The industry is also eagerly awaiting funding decisions for the other five R & D projects, but the final funding amount (a total of $1.6 billion) has not been announced.
APPF will invest in an integrated advanced packaging manufacturing process so that new technologies can be verified at a commercial - scale packaging level. Verifying the feasibility of innovation in this facility will significantly reduce the risks in the technology - development process and enable it to be more efficiently integrated into commercial advanced packaging operations. As the APPF program develops, continuous cooperation with the industry is needed to ensure the successful establishment of a strong U.S. advanced packaging industry at this facility.
Innovation across the Entire Semiconductor Technology Stack
Innovation in the semiconductor industry increasingly emphasizes collaboration. The NSTC aims to establish long - term R & D resources for the entire U.S. semiconductor ecosystem, enabling established industry players, startups, and academia to achieve broad success domestically. For decades, computer hardware innovation and computer software innovation have been in relatively independent cycles. Hardware suppliers manufacture more powerful processors by integrating more transistors, while software suppliers write programs to execute customers' computing workloads.
Today, the industry heavily relies on new "full - stack" solutions to better customize hardware and software and ultimately deliver integrated systems with higher performance and efficiency. This innovation strategy has proven effective, but it requires increased collaboration among participants across the entire computing stack and the entire value chain. Other regions (such as Europe, Japan, Taiwan (China), Singapore, and the Chinese mainland) have heavily invested in national semiconductor research alliances to promote such innovation, but the success and progress speed of the United States will depend on our ability to scale up collaborative innovation domestically using new environments, tools, and infrastructure.
The NSTC was established with the purpose of "conducting research and prototyping of advanced semiconductor technologies and developing the domestic semiconductor workforce to enhance the economic competitiveness and security of the domestic supply chain" (15 U.S.C. 4656(c)). Congress instructed the NSTC to operate in the form of a "public - private partnership alliance", involving both the private sector and federal research institutions. To ensure the long - term success of the NSTC and obtain continuous industry support, its operations must continuously respond to industry technology priorities.
The U.S. Department of Commerce designated Natcast (National Semiconductor Technology Center of the United States) as a dedicated non - profit organization to operate the NSTC and provided $6.3 billion in funding through a long - term grant agreement. The three overall goals of the NSTC are:
• Expand the United States' technological leadership;
• Reduce the time and cost of prototyping and manufacturing;
• Establish and maintain a semiconductor workforce - development ecosystem.
As a public - private partnership project, the work of the NSTC is jointly guided by the U.S. Department of Commerce and an expert technical advisory committee composed of top technical experts from all aspects of the semiconductor supply chain. To provide the infrastructure required to achieve these goals, the NSTC is building three main facilities, which are briefly introduced below. For a more detailed description, please refer to Appendix II.
1. Prototyping and Advanced Packaging Pilot Facility: The NSTC is committed to scaling up new manufacturing and advanced packaging technologies to make them commercially viable and promoting the "lab - to - fab" transformation. New technologies usually start in academia and are demonstrated on a small scale and with low production volume. Once the proof - of - concept is completed, a large amount of development work must be carried out to mature the technology for deployment in the commercial market. In fact, the value of a new technology cannot be evaluated without sending wafers through a fully integrated manufacturing process and measuring their overall performance. The Prototyping and Advanced Packaging Pilot Facility will provide a complete, integrated manufacturing process for this capability. The facility will be located in the Arizona State University Research Park. Preliminary plans call for it to start at Arizona State University in 2026, and the new facility will be completed by the end of 2028.
2. EUV Accelerator: Extreme ultraviolet (EUV) lithography technology has proven to be an indispensable and important tool for manufacturing advanced semiconductors. The continuous development of EUV lithography technology (and its successor, high - numerical - aperture (NA) EUV lithography technology) is crucial for the industry to keep up with the development of cutting - edge manufacturing technologies. At the same time, the related industries that support lithography technology must also advance their technologies in tandem. The mission of the National Semiconductor Technology Center (NSTC) EUV Accelerator is to make the use of this important tool more accessible and support the entire industry in jointly developing innovations to bring new EUV technologies to the market faster. This facility is expected to be operational in the summer of 2025.
3. Design Collaboration Facility (DCF): Determining the layout of billions of transistors on a wafer to execute large - scale computing tasks is an extremely complex task. The design segment of the semiconductor value chain includes companies that develop electronic design automation (EDA) software, IP providers that assemble design - module libraries for chip design, and fabless companies that use EDA software and IP modules to design complete chip systems. DCF will support design R & D and be equipped with a new "design - enable gateway" to lower the threshold for chip startups by providing centralized access to EDA software and databases. By leveraging the collective purchasing power of the National Semiconductor Technology Center (NSTC) and its members, DCF will accelerate the R & D process and significantly reduce the growing costs associated with the design and development of experimental chips and architectures