HBM has hit a wall.

If we were to use one word to summarize the evolution of HBM in recent years, it would be: stacking higher and higher. In essence, HBM is a storage technology that “vertically stacks DRAM”. The higher the number of layers, the larger the capacity and higher the bandwidth of a single HBM chip, which is even more appealing for AI GPUs – because what AI truly lacks has never been computing power, but the speed of feeding data.

Therefore, the evolution path of HBM is also very clear: from 4 layers to 8 layers, 12 layers, and approaching 16 layers. The 8 - layer HBM is the mainstream for true maturity and large - scale shipments. It has been the “most common configuration” for AI GPUs in the past. It has a stable yield rate and the most mature supply chain. The 12 - layer HBM has become the main mass - production direction in the past two years, achieving a more ideal balance between capacity, performance, and cost, and is most suitable for large - scale shipments. As of now, HBM has officially entered the eve of mass production of 16 - layer stacking: at the just - concluded CES 2026, SK Hynix exhibited the world's first 16 - layer HBM4 sample, with a single - stack capacity increased to 48GB.

However, increasing the number of layers is not as simple as “stacking a few more layers”. In fact, every time the number of layers increases by 4, the manufacturing difficulty of the entire system significantly escalates: placement accuracy, solder joint spacing, Z - direction height control, warpage, underfill (MUF) reliability... All the problems that could originally be masked by process margins will be magnified to a “life - and - death” level by the height of 16 layers.

Facing this dilemma, the industry has split into two voices: one is to pursue an ultimate revolution, and the other is to make improvements based on reality.

Hybrid Bonding:

A Revolution Temporarily Blocked by “Standards”

Chip stacking mainly tests the packaging capabilities. In the advanced packaging circle in the past two years, a term has been extremely popular: Hybrid Bonding. It is an advanced interconnection technology that completely abandons solder and flux. Through the simultaneous bonding of the metal layer and the dielectric layer, it achieves an interconnection form closer to “direct connection”. It represents the ultimate direction of smaller interconnection spacing, higher I/O density, and even approaching “atomic - level connection”.

General HBM structure. Micro - bumps are shown in the figure. After adopting hybrid bonding technology, the gaps between DRAM chips will disappear. (Source: semiengineering)

Originally, the industry generally predicted that HBM4 would be the commercial debut of hybrid bonding. However, a recent revision by the JEDEC organization – relaxing the upper limit of the HBM module height from 720µm to 775µm – has spared a precious 55µm of space for the 16 - layer HBM to continue using the traditional micro - bump technology.

This standard bonus has given the previously tight physical limits some breathing room and has also pushed a technology called Fluxless (flux - free) into the spotlight.

Fluxless:

A Transitional Technology Before Reaching the Endgame

However, even with the height redundancy and without the immediate need for hybrid bonding, the problems still remain: the stability and cost structure of traditional interconnection processes can hardly support the mass - production ramp - up of 16 - layer HBMs.

Why? Let's zoom in on the key process in HBM stacking assembly – Thermo - Compression Bonding (TCB). Under various advanced packaging architectures, Thermo - Compression Bonding (TCB) is considered one of the most advanced interconnection methods. Although this technology has been developed and applied for more than a decade, due to the many benefits it brings when introduced, it is still being continuously adopted in new applications. It should be noted that TCB is not just for HBM; it is a key means to forcibly “stitch” Chiplets from different nodes together.

Thermo - Compression Bonding (TCB) emerged as a solution for finer - pitch applications. TCB uses wafers equipped with copper pillars (Cu Pillar) and solder caps (Solder Cap). By limiting the amount of solder, it reduces the spacing between copper pillars, thereby achieving higher interconnection density. There are various types of TCB (as shown in the figure below). Regardless of the type, the main method is to perform local solder reflow while fixing the chip and the substrate, and then cool the solder to solidify it, thus fixing the chip on the substrate. Usually, the chip is released only after the solder is partially or completely solidified. This method achieves higher accuracy because it does not rely on the self - alignment effect of the solder. At the same time, by keeping the chip and the substrate flat during the bonding process, it alleviates the warpage problem. In addition, TCB allows active control of the bonding layer thickness (BLT), ensuring a uniform shape of the interconnection solder and facilitating subsequent processes such as underfill.

The four main types of TCB include: Capillary Underfill TCB (TC - CUF), Molded Underfill TCB (TC - MUF), Non - Conductive Paste TCB (TC - NCP), and Non - Conductive Film TCB (TC - NCF) (Source: BESI)

Traditional TCB relies on flux and reflow to promote solder wetting and remove the oxide layer. However, in fine - pitch bonding, especially for pitches below 40μm, this method often leads to voids, residual contaminants, and reduced reliability, making it difficult to meet the requirements for higher precision. With the 16 - layer HBM4 compressing the interconnection spacing to the 10µm level, these problems will be further magnified: the residual and cleaning costs of the flux system begin to become a bottleneck for yield and reliability, and may even affect the wetting and adhesion of subsequent MUF/underfill materials.

Therefore, before truly moving towards hybrid bonding, the industry urgently needs a practical path that does not overthrow the existing TCB system but can transition to finer pitches (usually in the range of 10µm to 25µm) and higher stacking – Fluxless (flux - free) TCB has stepped into the spotlight in this context.

As the name suggests, this method does not use any form of flux. In flux - free TCB, the chip with copper pillars and solder caps is directly bonded to the substrate without any intermediate medium. However, oxide removal has become a core issue because the oxide layer inhibits the wettability of the solder and prevents it from forming a metallurgical bond with the base material. This process must ensure that all existing oxide layers are removed before the chip contacts the substrate and prevent the formation of new oxides during the TCB heating process.

In terms of oxide removal, ASMPT uses plasma activation (AOR: Active Oxide Removal) to replace chemical flux. This “dry” process can ensure an extremely clean interface, significantly reducing signal loss and improving thermal performance. Besi prefers formic acid and hydrogen - based reduction. Regardless of the technical path, the development of flux - free TCB (Fluxles TCB) represents a major advancement, addressing the limitations of flux and thin films in achieving a stable and reliable bonding process.

Source: ASMPT

ASMPT believes that in the next - generation HBM (as shown in the figure below), Flux - TCB has qualified for HBM mass production and has been used in HVM (High - Volume Manufacturing) for up to 12 layers; while AOR TCB has demonstrated the ability to be successfully implemented in the range of 12 - 16 layers, further supporting the HBM roadmap. This proven ability ensures that, while covering all layers, the gap height of the stacked chips can be strictly controlled, thus enabling the next - generation HBM – which is the key to meeting the performance requirements of the latest HPC and AI devices.

HBM roadmap planning (Source: ASMPT)

It can be said that Fluxless is both the ultimate squeeze of traditional soldering processes and the best “optimal solution” for equipment manufacturers to balance performance and yield in the mass production of AI chips before hybrid bonding completely dominates the battlefield.

SK Hynix:

It's Too Early for Fluxless Technology

However, even as a transitional solution, the Fluxless solution has not been smooth sailing in the process of mass production.

As the leader in HBM, after months of evaluation of Fluxless, SK Hynix gave a rather conservative conclusion: “It's still too early.” It is reported that SK Hynix will continue to use its proud Advanced MR - MUF process in its 16 - layer HBM4/4E products.

SK Hynix's MR - MUF process is a method of injecting a liquid packaging protection material into the inter - layer gaps after the chips are stacked and then curing it. The company jointly developed and improved the key MUF material with Namics of Japan and applied it to the third - generation HBM2E. SK Hynix believes that compared with the TC - NCF process of its competitors, which requires laying a film - like material every time a chip is stacked, MR - MUF is more efficient. Subsequently, SK Hynix introduced a new protective material and improved the heat - dissipation characteristics, and introduced “Advanced MR - MUF” into HBM3, which has been used in 12 - layer HBM4 products.

Source: SK Hynix

However, in SK Hynix's current MR - MUF process, flux still needs to be applied to remove the oxide film around the micro - bumps; if there are residues after cleaning, it may affect the yield – this is also one of the important reasons why Fluxless is being studied.

According to a report from Dealsite, a relevant person in the semiconductor industry said: “SK Hynix started a formal evaluation of introducing Flxless bonding in the 16 - layer HBM4 from the fourth quarter of last year. Although it had previously placed an order with ASMPT for TC Bonding equipment to support Fluxless, the evaluation results show that, given the current yield pressure and cost balance, the inertia of mature processes is still strong.

This “too early” also means that Fluxless has encountered more difficult real - world problems than expected in the mass - production stage.

Logically speaking, if even the “transitional” Fluxless TCB is being treated with caution and its introduction is postponed in the HBM4/16H generation, then the pace of full - scale large - scale implementation of the more ultimate interconnection technology – hybrid bonding – in the HBM system will probably be even more conservative. Hybrid bonding is not only expensive but also requires the reconstruction of new equipment, materials, and testing processes; the single - package cost of the first products using it will inevitably increase (although the increase in capacity may dilute the cost per bit). Therefore, this trend is more like a reminder to the industry: the direction of hybrid bonding will not change, but the timeline for “moving from the roadmap to large - scale mass production” may be extended.

This change in the rhythm of the interconnection route is not only happening in technical papers and roadmaps but is also being transmitted to the equipment procurement level.

Divergence Among Equipment Manufacturers

With the relaxation of the standard height of the 16 - layer HBM4, the bonding equipment market is no longer a simple “full - speed sprint” but has evolved into a deep confrontation regarding technical rhythm, mass - production yield, and supply - chain game.

1. BESI: A “Believer in the Endgame” of Hybrid Bonding

In the global equipment chain, BESI is often regarded as a “weather vane” for the industrialization of hybrid bonding. BESI firmly believes that as the I/O density continues to increase and the physical limits of micro - bumps are approaching, true 3D integration must move towards large - scale hybrid bonding. Therefore, BESI's technical and market strategies are more inclined to “seize the endgame in advance” – polishing the rhythm, accuracy, and platform capabilities of hybrid bonding as early as possible, waiting for the critical point of the HBM5 or 20 - layer + era to arrive. It should also be emphasized here that BESI is not only betting on hybrid bonding. In the reality where HBM4 still mainly uses micro - bumps/TCB, BESI also has key product lines such as thermo - compression bonding and high - precision placement.

However, the correctness of the endgame cannot smooth out short - term fluctuations. JEDEC's leniency towards the height of the HBM4 module has given the micro - bump technology a longer lifespan, and has also forced BESI to face the risk of being “a pioneer when leading half a step and a martyr when leading one step”. The total order amount of BESI in the first three quarters of 2025 (434.6 million euros) decreased by 6.5% year - on - year, revealing that the introduction rhythm of hybrid bonding is slower than expected. Although BESI received the expected HB orders in the fourth quarter, it may be experiencing a difficult “watch before dawn”.

2. ASMPT: A “Realistic Evolutionist” of TCB

Compared with BESI, ASMPT is more like a “realistic engineering school” in the HBM industrial chain: it does not deny the importance of hybrid bonding but emphasizes that in the current mass - production window period, TCB is still the core process platform for HBM stacking – especially in the transition stage from 12 layers to 16 layers.

The Fluxless direction promoted by ASMPT (such as AOR: Plasma - Assisted Oxide Removal) essentially answers a mass - production question: how to make the interface cleaner, more stable, and more reproducible without overthrowing the micro - bump/TCB system? This route is more easily downward - compatible with existing production lines and is closer to the immediate KPIs of customers: yield, rhythm, TCO, and reliability.

In terms of performance, the revenue share of ASMPT's advanced packaging business increased to approximately 39% (approximately $326 million) in the first half of 2025, clearly driven by AI demand. More notably, it has continuously increased its TCB orders: on December 3, 2025, ASMPT announced that it had received 19 new orders for chip - to - substrate (C2S) TCB from a major OSAT partner of a leading foundry; on December 22, 2025, ASMPT announced that it had additionally received 15 orders for C2S TCB equipment for cutting - edge AI computing chips.

At the same time, ASMPT expects that by 2027, the total potential market size (TAM) of TCB will exceed $