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With the development of digitalization, embedded systems have become the core supporting the operation of smart devices. From real-time health monitoring of wearable devices to environmental perception of autonomous vehicles, from precise control of industrial robots to high-speed data processing of 5G base stations, these scenarios have put forward increasingly stringent requirements for the performance, power consumption, and cost of memory. Traditional storage technologies are gradually showing their shortcomings: although Static Random Access Memory (SRAM) can provide high-speed access, its high cost and limited capacity make it difficult to meet the needs of large-scale data processing; while Dynamic Random Access Memory (DRAM) has a high storage density, it requires complex refresh circuits, and the problem of power consumption control has always restricted its in-depth application in the embedded field.
In this case, Pseudo Static Random Access Memory (PSRAM) stands out with its unique technical architecture and becomes a new choice in the field of embedded memory. This innovative product that combines the interface convenience of SRAM and the storage density advantage of DRAM is reshaping the market pattern of embedded storage.
01
What is PSRAM?
PSRAM (Pseudo Static Random Access Memory) is a new storage solution designed for embedded systems, consumer electronics, IoT (Internet of Things), wearable devices, and edge-side AI products. As the name suggests, it is a type of DRAM that simulates the operating characteristics of SRAM through technical means.
To understand the advantages of PSRAM, we need to first understand the characteristics of traditional memories. Although SRAM is fast and has a simple interface, it requires six transistors to store one bit of data, resulting in high cost and low density. DRAM has high density and low cost, but it requires a complex controller for periodic refresh, which increases the system complexity. PSRAM cleverly combines the advantages of both: it uses a storage structure similar to DRAM with one transistor and one capacitor, while maintaining a simple interface similar to SRAM.
Structurally, PSRAM uses the same 1T+1C (single transistor + single capacitor) storage unit as DRAM inside. This structure enables it to achieve a storage density comparable to that of DRAM - under the same process, the capacity of PSRAM can reach 4 - 8 times that of SRAM. However, different from traditional DRAM, PSRAM integrates a self-refresh controller and related logic circuits inside the chip, which can automatically complete the data refresh operation without the intervention of an external controller, making its external interface characteristics fully compatible with SRAM.
This architectural design brings significant system-level advantages. For embedded developers, PSRAM can be directly connected to the address bus and data bus of a microcontroller (MCU) or microprocessor (MPU) like SRAM, without the need to design additional complex refresh control logic, which greatly reduces the difficulty of hardware design and software development complexity.
In the current market, many well-known manufacturers have launched MCU products that support PSRAM. Infineon's TRAVEO series, NXP's i.MX RT series, Renesas' R-CAR series, etc. all provide PSRAM solutions.
02
What does PSRAM bring?
In the technical landscape of embedded storage, PSRAM does not exist in isolation but forms complementary and competitive relationships with technologies such as SRAM, DRAM, and NAND Flash. In-depth analysis of the advantages and disadvantages of PSRAM compared with these technologies helps to understand its market positioning and application scenarios.
Currently, the mainstream types of PSRAM include OPI PSRAM, QPI PSRAM, and SPI PSRAM, among which OPI PSRAM is the most typical. The design concept of this type of memory revolves around "replacing parallel with serial". For example, OPI PSRAM uses an 8-bit serial data line and can reach a theoretical bandwidth of 2.128Gbps through the DDR mode at a clock frequency of 133MHz. Its 24-pin package significantly simplifies the circuit design compared with the 40+ pins of traditional DDR SDRAM. Models such as APS12808L-OBM-BA of A-Pulse Technology have been commercially available, supporting a throughput of 266MB/s in Xccela mode, which is particularly suitable for scenarios in IoT devices and wearable devices that need to balance bandwidth and volume.
There are also QPI and SPI types that form a gradient coverage with OPI PSRAM. The former is compatible with the SPI protocol through 4 bidirectional data pins and provides a bandwidth of 416Mbps at a frequency of 104MHz; the latter uses the standard SPI interface and is suitable for cost-sensitive applications with an 8-pin micro package. The common advantage of these variants is that they get rid of the dependence on complex controllers of traditional DDR SDRAM. For example, they do not require a dynamic refresh mechanism and directly adopt an SRAM-like interface protocol, which significantly reduces the development threshold. In terms of power consumption management, the new PSRAM supports intelligent refresh technologies such as PASR (Partial Array Self Refresh), which can ensure data integrity and reduce the standby power consumption to the microampere level, which is crucial for battery-powered smart voice devices or industrial sensors.
From the perspective of application scenarios, this type of memory is rapidly replacing DDR in the fields of mobile communication, real-time control systems, and edge computing. The voice coprocessor in smartphones often uses OPI PSRAM as an audio stream buffer, and its read latency is about 30% lower than that of DRAM; industrial robotic arms achieve instant access to motion trajectory data by integrating QPI PSRAM, avoiding the response latency caused by the DRAM refresh cycle in traditional solutions. It is worth noting that although the absolute bandwidth of PSRAM has not reached the level of high-end DDR4/DDR5, its breakthrough in unit pin efficiency (such as the transmission efficiency of each pin of the OPI interface reaching 266Mbps) is redefining the design paradigm of embedded storage, especially in scenarios where the PCB space is limited but continuous data streams such as images and voices need to be processed, showing unique competitiveness. This technological evolution essentially seeks a new balance point that better meets the needs of emerging markets among performance, power consumption, and cost through interface protocol innovation and storage unit optimization.
However, PSRAM also has inherent technical limitations. As a volatile memory, PSRAM will lose all data after power-off, so it cannot independently undertake the task of persistent data storage and must be used in conjunction with non-volatile storage such as NAND Flash. In scenarios such as smart home control panels, a combination scheme of "PSRAM + NOR Flash" is usually adopted: PSRAM is used to run the real-time operating system and cache temporary data, while NOR Flash is used to store firmware and user configuration information. Although this combination increases the system complexity, it balances performance and data security.
Capacity limitation is another major challenge faced by PSRAM. Currently, the capacities of mainstream PSRAM products on the market are mostly between 32Mb and 512Mb. The highest-end Infineon HYPERRAM™ product has a capacity of 512Mb, which is significantly lower than the 16Gb capacity of DRAM products such as LPDDR5. This capacity bottleneck makes it difficult to apply in scenarios that require large-scale caching, such as high-end in-vehicle infotainment systems and edge computing nodes.
03
Domestic breakthrough: From technology follow-up to market breakthrough
The self-controllable strategy of China's semiconductor industry provides a historical opportunity for the localization of PSRAM.
Recently, the breakthrough of Unisoc in the field of PSRAM is of symbolic significance. In July 2025, the company released a full range of PSRAM products compatible with the Xccela protocol, with capacities covering 32Mb, 64Mb, and 128Mb. They use a BGA24L ultra-thin package and also support the KGD product form. This series of products can provide storage solutions for IoT devices, wearable electronic products, and edge-side AI products.
The PSRAM chips of Unisoc are compact in size, support the industry's highest speed of 400MHz, and the transmission rate is increased to 1066Mbps, achieving a high-bandwidth performance of up to 17.06Gb/s. They also support the online dynamically configurable X8 and X16 modes to adapt to the needs of different applications. To meet the strict requirements for long battery life, Unisoc's PSRAM supports low-power designs including Half Sleep. The products on the market support a voltage range of 1.62 - 1.98V, including 1.8V low-voltage power supply. The upcoming 256Mb (32MB) large-capacity version also supports dual voltages of 1.8/1.2V and ultra-low-power modes such as dynamic voltage change of 0.9V. In addition, it also supports high reliability in the industrial-grade wide temperature range from -40°C to 105°C.
From the perspective of product planning, Unisoc is promoting technological iteration with the logic of "application-driven innovation": in addition to the specifications below 128Mb that have been released, the new 256Mb product has entered the tape-out stage and is planned to be mass-produced in Q4; in terms of packaging technology, a CSP (Chip Scale Package) solution will be launched later to further adapt to ultra-miniature devices such as TWS earphones. This technological layout not only fills the gap in high-performance and low-power PSRAM in China but also is expected to break the long-term dominance pattern of Japanese and Korean enterprises in the global IoT storage market. In terms of price, the 32Mb version costs 16 yuan, and the 128Mb version costs 25 yuan.
In addition, among domestic MCU camps, the products with integrated PSRAM are as follows:
GD32E5 series MCU of GigaDevice: It integrates 4MB PSRAM on-chip.
Model3 chip of Qimingzhixian: The Model3 chip is a high-performance display interaction and intelligent control MCU, which has an on-chip 1MB large-capacity SRAM and 64Mb PSRAM built-in.
ButterFliSF32LB557 of Siche Technology: The SF32LB55x series is a series of highly integrated and high-performance system-on-chip (SoC) MCU chips for ultra-low-power artificial intelligence IoT (AIoT) scenarios, which integrates 4MB PSRAM.
AG32 series of AGM (AOGEM): The new AG32 series MCU products are integrated with 64Mb PSRAM, which is suitable for customers with large in-chip RAM requirements.
Looking forward to the future, with the further popularization of IoT and artificial intelligence applications, the demand for MCU storage capacity will continue to grow. As a storage solution that balances cost, performance, and ease of use, PSRAM will surely be more widely used. By directly integrating PSRAM in the MCU, it provides a more convenient solution for users, representing an important direction for the future development of MCUs.
For China's semiconductor industry, the development of PSRAM technology is both an opportunity and a challenge. On the one hand, we can see that more and more domestic MCU manufacturers are starting to integrate PSRAM in their products, showing a strong momentum of technological catch-up; on the other hand, there is still a gap compared with international leading enterprises in high-end PSRAM technology. However, with the continuous emergence of innovative products, it is believed that domestic MCUs will gradually narrow the gap with the international level in PSRAM applications.
Generally speaking, PSRAM brings larger storage space, better cost-benefit ratio, lower power consumption, and simpler system design to MCUs. These advantages make PSRAM an indispensable part of modern MCU design. With the continuous progress of technology and the continuous growth of application requirements, we have reason to believe that PSRAM will play a more important role in future MCU design.
This article is from the WeChat official account “Semiconductor Industry Insights” (ID: ICViews), author: Pengcheng, published by 36Kr with authorization.