FD-SOI, challenging 7nm, what makes it possible?

Eight years ago, GlobalFoundries announced that it would stop the R&D of 7nm FinFET process. Eight years later, this wafer foundry is trying to re-enter the competition of advanced logic processes through another technical route.

In an interview with Tom's Hardware, Sudipto Bose, Vice President of GlobalFoundries' FD-SOI business unit, elaborated on the company's new-generation FDX Fusion process. Based on FD-SOI (Fully Depleted Silicon-On-Insulator), this technology adopts advanced planar transistors without EUV lithography, aiming to achieve 7nm-level power consumption and performance while reaching 8nm-level logic density.

This is not a 7nm process in the traditional sense. According to the data released by GlobalFoundries, the logic density of FDX Fusion is 14 million logic gates per square millimeter, which is equivalent to about 56 million transistors/mm² (calculated based on 4 transistors per logic gate for a 2-input NAND gate).

The main basis for GlobalFoundries to position it at the 7nm level is not the transistor density, but the power consumption and performance that the chip can finally achieve.

This also reflects GlobalFoundries' positioning of FDX Fusion: instead of competing head-on with traditional advanced FinFET processes for transistor density, it provides competitive performance without using EUV and reduces chip design and manufacturing costs as much as possible through innovations in FD-SOI structure, materials and processes.

Breaking the Performance Boundary of Traditional Processes

GlobalFoundries did not just start investing in FD-SOI technology now.

Sudipto Bose said that the company has continued to invest in this field for nearly eight years. At present, GlobalFoundries' 22FDX and 22FDX+ platforms have gained a considerable number of customers, and products from more than 90 customers are entering the production ramp-up stage.

This is also an important reason why GlobalFoundries continues to develop FDX Fusion.

The biggest difference between FD-SOI and traditional FinFET lies in the transistor structure. It uses an ultra-thin silicon layer and a buried oxide layer (BOX) to achieve full depletion by controlling the thickness of the channel silicon layer. Compared with traditional bulk silicon processes, this structure has low power consumption and good back gate control capability.

Among them, Adaptive Body Bias (ABB) is an important technical advantage of FD-SOI. By adjusting the voltage applied to the transistor body region, the threshold voltage of the transistor can be changed: forward body bias can reduce the threshold voltage and improve performance, while reverse body bias can increase the threshold voltage and reduce leakage power consumption.

This capability allows the chip to dynamically adjust between performance and power consumption according to different workloads.

GlobalFoundries believes that the potential of FD-SOI does not end at the 22nm process node. FDX Fusion aims to further improve digital logic density, radio frequency performance and memory integration capability on the basis of retaining the original technical advantages.

Sudipto Bose even gave an example: current 22FDX in some applications, although the logic gate density does not reach the level of 16nm process, has reached the 16nm level in system indicators such as CPU frequency and performance per watt, and even can reach the 12nm level in some cases.

This is also how GlobalFoundries understands process node competition: transistor density is important, but whether the final chip can meet the system requirements for performance, power consumption and area is equally important.

Core Technologies of FDX Fusion

Then, how does FDX Fusion further improve performance on the traditional FD-SOI structure?

The first is the transistor itself.

Sudipto Bose revealed that GlobalFoundries is cooperating with Soitec and CEA-Leti to develop strained silicon substrates for FDX Fusion under the FAMES project.

Since FD-SOI relies on special silicon-on-insulator wafers supplied by Soitec, the three parties are studying how to introduce strain into these substrates to improve the mobility of charge carriers, thereby enhancing transistor performance.

At present, this solution has been proven feasible in the laboratory, and partners are further improving the manufacturing process to prepare for mass production.

In addition to substrate materials, GlobalFoundries is also carrying out multiple performance optimizations for PFET and NFET.

Sudipto Bose revealed that the R&D investment of FDX Fusion is roughly divided into two parts: about 50% is used for the transistor itself, and the other 50% is used for the optimization of Contacted Poly Pitch (CPP) and metal layer pitch.

The latter two are directly related to the density of transistors and interconnection structures. GlobalFoundries is further reducing relevant dimensions through more advanced patterning technology, lithography process and gate oxide engineering.

In terms of lithography route, FDX Fusion still uses DUV instead of EUV. In order to achieve the target gate and metal pitch, critical layers are expected to require multi-patterning technology.

GlobalFoundries has not yet released specific CPP and metal pitch data. Sudipto Bose said that this involves certain technical IP, and the company hopes to complete the first batch of silicon wafer verification before gradually releasing it to customers.

This also shows that FDX Fusion is not simply scaling down the existing 22FDX process, but requires systematic upgrades in multiple links such as transistors, substrates, lithography and interconnections.

Why Dare to Call It 7nm-Level Performance?

The most noteworthy part of FDX Fusion is that it adopts a different definition method between logic density and performance.

GlobalFoundries announced the target of 14 million logic gates per square millimeter. According to the conversion method of 2-input NAND gates, it is equivalent to about 56 million transistors/mm², which is close to Samsung's 8nm-level process.

Then why does GlobalFoundries not directly call it 8nm, but position it as 7nm-level?

Sudipto Bose explained that logic gate density mainly determines the physical size of the chip, but cannot fully reflect the actual performance of the chip. In addition to improving logic density, FDX Fusion also retains the adaptive body bias capability of FD-SOI, and optimizes standard cells and metal interconnections.

GlobalFoundries hopes that the final chip can reach or even exceed the performance of traditional 7nm process in indicators such as TOPS/W.

In terms of power consumption and performance, the company also gave relatively clear goals: based on the existing generation of FDX platform, FDX Fusion hopes to achieve 30% performance improvement and 40% power consumption reduction. If compared with standard cores, it hopes to achieve at least 20% improvement.

Of course, these are all current R&D goals of GlobalFoundries, and the final performance still depends on specific applications and chip designs.

From this perspective, the 7nm-level positioning of FDX Fusion does not claim that it has the same transistor density as traditional 7nm FinFET, but hopes to obtain similar comprehensive performance through different technical combinations.

Not Chasing General-Purpose CPUs

From the perspective of application direction, GlobalFoundries does not position FDX Fusion as a manufacturing platform for general-purpose CPUs or large-scale AI computing chips, but hopes to continue to strengthen its advantages in the fields of connectivity, radio frequency and low-power chips.

The first is connectivity chips, including applications such as Wi-Fi, Bluetooth, cellular communication and satellite communication. These fields have always been important markets for GlobalFoundries' FD-SOI, and FDX Fusion hopes to meet higher data transmission demands by further improving radio frequency performance.

Sudipto Bose specifically mentioned the fT/fmax index of 500GHz, that is, the cutoff frequency and maximum oscillation frequency of the transistor. This capability is very important for high-frequency RF circuits, and also enables FDX Fusion to target higher-performance connectivity applications.

Automotive radar is also one of the key markets. GlobalFoundries currently has a large number of radar businesses in the automotive field, especially 81GHz related applications. With the improvement of FDX Fusion performance, the company hopes to help customers further expand their automotive radar product portfolio, and also include automotive MCUs in the target market.

Edge AI is another important layout.

Sudipto Bose used four links: Sense, Think, Act and Connect to describe physical AI.

For example, humanoid robots and automobiles need to perceive the surrounding environment through the vision system, and then use the reasoning chip to understand the environment and make judgments; speech recognition chips need to receive sound, recognize semantics and complete corresponding reasoning.

These applications do not necessarily require the computing power of large data centers, but have high requirements for power consumption, real-time response and local reasoning capability. FDX Fusion hopes to provide process support for these edge vision processing, speech recognition and reasoning chips.

In the field of data centers, GlobalFoundries' focus is also not on CPUs, but on data connectivity and signal processing.

Specifically, the inside of the data center needs to complete the conversion between electrical signals and optical signals through silicon photonics technology. After the receiving end converts the optical signal into an electrical signal, it also needs to process the weak electrical signal through an amplifying circuit before transmitting it to the computing chip.

At present, GlobalFoundries uses silicon germanium process to provide such amplifying circuits, and FDX Fusion will also become another process option for customers in the future.

Sudipto Bose specifically mentioned applications from 100Gbps to 200Gbps per wavelength, as well as designs such as TIA (Trans-Impedance Amplifier) and clock recovery circuits.

This shows that GlobalFoundries hopes to extend the application scope of FD-SOI from traditional low-power chips to high-speed data center interconnection.

No EUV Used to Reduce Costs

If performance is the technical goal of FDX Fusion, then cost is another competitive advantage that GlobalFoundries hopes to establish.

Traditional advanced processes at 6nm and 7nm levels require the use of EUV lithography equipment, and related equipment investment and mask costs are relatively high.

FDX Fusion uses DUV lithography and advanced planar transistors, no EUV equipment is required, which gives GlobalFoundries the opportunity to provide a process platform with more competitive costs.

Sudipto Bose said that the mask cost of FDX Fusion is expected to be significantly lower than that of 6nm-level processes, and customers do not have to bear the same level of tape-out costs.

This is especially important for markets that require a large number of dedicated chips such as edge AI and automotive electronics.

Unlike large general-purpose processors, edge devices often need to design dedicated chips for different applications. One chip can hardly cover all applications, and customers may need to develop separate chips for different products.

If every tape-out requires a mask cost of millions of dollars, the economic pressure of developing multiple dedicated chips will be relatively high.

GlobalFoundries hopes to lower this threshold through FDX Fusion, allowing customers to perform multiple tape-outs for different applications without having to bear the same design costs as traditional advanced nodes.

However, not using EUV does not mean that FDX Fusion is less difficult to manufacture.

Sudipto Bose admitted that this will be one of the most advanced planar transistor processes in the world, and its manufacturing complexity is significantly higher than the current 22nm-level FD-SOI production line, and also higher than GlobalFoundries' 12nm FinFET process.

The company is cooperating with equipment suppliers to find an equipment combination that can meet the process requirements and achieve stable yield.

In terms of equipment investment, FDX Fusion still needs to introduce new equipment, but GlobalFoundries hopes to reuse existing equipment as much as possible in the front-end transistor manufacturing link.

The company's goal is to make the operating cost of FDX Fusion significantly lower than that of traditional 7nm or 6nm-level processes. As for how big the final cost advantage is, it needs to be further determined after the wafer fab completes internal process verification.

Achieve Mass Production in 2030

From the perspective of commercialization progress, GlobalFoundries has given a clear time plan.

The company plans to provide the first version of FDX Fusion PDK (Process Design Kit) in mid-2027, allowing customers and the design ecosystem to start chip design.

In 2028, GlobalFoundries hopes to launch initial customer production. Sudipto Bose specially emphasized that this refers to initial customer production, not mass production.

As for high yield and meaningful production scale, the company's goal is to achieve mass production in 2030.

At present, some customers have promised to develop chips based on this technology, but GlobalFoundries still needs to deliver products that meet customer specifications first.

The interview also mentioned companies such as BMW, Bosch, NXP, Siemens and Tesla. Sudipto Bose said that these industry chain related companies have been promoting GlobalFoundries to develop similar technologies and put forward corresponding demands in the past few years. Now the company needs to prove that it can deliver a technology platform that meets these requirements.

In terms of EDA and IP ecosystem, GlobalFoundries has held discussions with major EDA vendors, which is currently in the RFI/RFQ stage, and relevant communications have lasted for about six to nine months.

In the first two years, the company will focus on cooperating with pilot customers to develop basic IP such as standard cells, I/O and SRAM. As for complex IP such as PCIe Gen 4/5, LPDDR6 and DisplayPort, they will be gradually improved according to the specific application needs of the first batch of customers.

In addition, GlobalFoundries also plans to use its internal MIPS and ARC processor IP resources to promote the construction of FDX Fusion ecosystem. Sudipto Bose revealed that MIPS will cooperate with the company to develop a platform optimized for physical AI, and adapt the existing processor IP to the FDX Fusion process.

He believes that having internal customers like MIPS can speed up the company's development cycle by 5 times, because MIPS can develop test chips earlier and provide feedback to the process team.

Still Exploring More Possibilities

FDX Fusion is defined by GlobalFoundries as the first-generation product, but the company has begun to consider the possible direction of next-generation technologies.

Sudipto Bose revealed that there are still some technologies in the innovation laboratory stage, including embedded non-volatile memory, EDA routing, Chip Folding and 2.5D integration. These technologies may become important parts of the next generation of FDX Fusion in the future.

However, the specific release time of the next-generation product has not yet been determined. GlobalFoundries expects that by the first half to mid-2028, with the gradual launch of the first batch of silicon wafer verification and customer feedback, the company will have a clearer judgment on the next-generation technical route.

It is worth noting that FDX Fusion is not a process platform simply developed based on the existing research results of CEA-Leti.

Sudipto Bose said that at present, except for the substrate engineering part which is jointly promoted by GlobalFoundries, Soitec and CEA-Leti, the rest of FDX Fusion mainly comes from GlobalFoundries' own technical accumulation, including the existing FDX platform, the previous 7nm project and the technologies accumulated during the 12nm process R&D process.

Judging from the information revealed in this interview, GlobalFoundries does not intend to return to the traditional competition method of advanced FinFET processes, but hopes to establish a different competition logic through FD-SOI: achieve higher performance with advanced planar transistors and special substrates, avoid EUV equipment investment through DUV process, and then attract customers in the fields of edge AI, automotive electronics and high-speed interconnection with lower design costs.

Whether this route can succeed depends ultimately on the performance of the first batch of customer products in 2028 and the mass production performance in 2030. But for FD-SOI, FDX Fusion at least provides a new development direction: it is no longer just a low-power characteristic process in the 22nm era, but also begins to extend to the higher-performance dedicated chip market.

This article is from the WeChat official account "Semiconductor Industry Watch" (ID: icbank), author: Editorial Department, released with authorization from 36Kr.