Packaging Substrate, Fierce Battle
Once a little-noticed segment in the semiconductor industrial chain, packaging substrates are now becoming a highly sought-after target amid the AI boom.
As demand for AI chips continues to rise and advanced packaging capacity keeps expanding, substrate supply is tightening, and issues related to delivery lead times and production capacity have gradually drawn attention across the industrial chain. According to a report released by Counterpoint Research in March 2026, affected by surging AI demand and rising complexity of high-end products, the supply-demand gap in the ABF carrier board industry may reach around 20%, and new production capacity will not be released in batches until 2027.
The changes come not only from growing demand: as GPUs, ASICs and HBMs are integrated into the same package, higher density interconnection between chips is required, and the design of power supply, signal transmission and heat dissipation inside the package has also become more complex. Traditional organic substrates are facing challenges in dimensions, flatness and fine circuits, which has put glass core substrates in the spotlight.
However, glass is not the only solution. Silicon interposers, silicon bridges and RDLs correspond to different packaging architectures and performance requirements respectively. Enterprises including TSMC, Intel, Samsung Electro-Mechanics and ASE are also advancing technical layouts along different routes.
This means that competition in the substrate field is no longer limited to material substitution between ABF and glass, but extends to packaging architecture, design tools, manufacturing processes and testing capabilities.
Substrate Materials: More Than One Option
To get a clear view of this competition, we have to return to the substrate itself. The packaging substrate connects the chip to the PCB mainboard, and undertakes functions such as signal transmission, power supply and mechanical support. As the integration level of GPUs, ASICs and HBMs increases, the packaging area keeps expanding, and the interconnection between chips becomes more intensive, putting forward higher requirements for the circuit accuracy, dimensional stability and warpage control of substrates.
At present, organic substrates are still an important foundation for high-end packaging. Build-up insulating materials represented by ABF can support the construction of multi-layer fine circuits, and are widely used in packaging substrates for high-performance CPUs, GPUs and other products. However, in large-size and high-density packaging, traditional organic core materials face greater pressure in terms of flatness and dimensional stability, making glass core substrates an important exploration direction.
Glass has good flatness, rigidity and dimensional stability, which is expected to support larger-size packaging and more refined circuit design. The market has high expectations for this route: industry reports released by SEMI and Global Net Corp. in 2026 predict that the compound annual growth rate of the glass core substrate market may reach 67.2% from 2028 to 2040.
However, the application of glass in packaging also needs to be distinguished: glass core substrates use glass to replace the core material in traditional organic substrates; glass interposers use glass to undertake high-density interconnection between chips; glass carriers are mainly used for temporary bearing during the manufacturing process.
In addition to material changes, the interconnection structure inside the package is also being adjusted. Silicon interposers can carry high-density interconnection, and TSMC's CoWoS-S adopts this solution. Intel's EMIB uses silicon bridges, which only needs to embed small silicon dies in key interconnection areas. In addition, RDL opens up connections between chips by redistributing metal circuits, and can also be combined with structures such as organic substrates.
It can be seen that organic substrates, silicon interposers, silicon bridges, RDLs and glass solutions are not in a simple substitution relationship, but form different combinations according to packaging size, interconnection density, cost and manufacturing maturity. The focus of substrate technology competition is shifting from material selection to the overall optimization of packaging architecture.
The Substrate Industrial Chain Is Undergoing a Collective Transition
The diversification of substrate technology routes has been reflected in the layout of major packaging enterprises. On the one hand, traditional substrate manufacturers are still expanding the production capacity of high-end organic substrates; on the other hand, wafer manufacturing and packaging enterprises are adjusting their interconnection architectures, and material suppliers have also started to promote the R&D and industrialization of glass core substrates.
Ibiden: Continuous Capacity Expansion for High-end Organic Substrates
The fact that glass core substrates have attracted attention does not mean that the competition for traditional organic substrates has ended. As demand for AI servers and high-performance chips grows, the existing production capacity of high-end substrates remains tight, and expanding the supply capacity of mature products is still an important task for leading manufacturers.
Japanese substrate manufacturer Ibiden is a representative case. In February 2026, Ibiden announced that it plans to invest about 500 billion yen in its electronics business between fiscal year 2026 and 2028, focusing on expanding the production capacity of high-performance IC packaging substrates for AI servers and high-performance servers. For the first phase, it plans to invest about 220 billion yen in the Kawajiri Plant in Gifu Prefecture, and the relevant equipment is expected to be put into operation and start mass production successively from fiscal year 2027.
This investment sends a signal: even if glass core substrates are regarded as an important direction for next-generation packaging, the current demand of AI chips for high-end substrates still needs to be met by mature organic substrate production capacity. For traditional suppliers like Ibiden, expanding production capacity and improving the manufacturing capability of high-layer and large-size substrates is still a practical path to seize the growth of the AI server market.
Samsung Electro-Mechanics: Extending from Organic Substrates to Glass Core
Different from Ibiden's continuous expansion of mature substrate production capacity, Samsung Electro-Mechanics is extending its existing substrate manufacturing capabilities to next-generation materials. As a high-end FC-BGA substrate supplier, Samsung Electro-Mechanics has accumulated manufacturing experience in large-size, high-layer and high-density circuit substrates. For Samsung Electro-Mechanics, glass core substrates are not only a technical reserve to meet the needs of next-generation packaging, but also an opportunity to extend its existing substrate manufacturing capabilities to higher-end products.
However, the transition from organic substrates to glass core substrates also requires supplementary process capabilities such as glass processing. To this end, the company chose to introduce technical resources from Sumitomo Chemical. In July 2026, Sumitomo Chemical disclosed that its Korean subsidiary Dongwoo Fine-Chem has signed a joint venture agreement with Samsung Electro-Mechanics, planning to establish a glass core substrate business company.
Subsequently, at the KPCA exhibition in September 2026, Samsung Electro-Mechanics demonstrated glass substrate technology, introducing processes such as forming fine connection vias on glass, metal filling and precision surface treatment. At the same time, the company also exhibited 2.5D and 2.1D packaging substrates for AI accelerators, demonstrating its technical progress in large-size, high-layer and high-density interconnection.
TSMC: Expanding Interconnection Design Around CoWoS
The form and performance requirements of substrates largely depend on the interconnection architecture adopted between chips. As the integration level of GPUs, ASICs and HBMs increases, relying solely on traditional packaging substrates can no longer meet some high-density interconnection requirements, making silicon interposers, RDLs and local silicon interconnection different technical options. TSMC's CoWoS series is exactly the representative of this change.
According to the company's official materials, CoWoS-S adopts a silicon interposer, which supports a maximum interposer area of about 2700 square millimeters, equivalent to about 3.3 times the reticle size; CoWoS-R uses an RDL interposer; CoWoS-L combines an RDL interposer with embedded local silicon interconnection (LSI).
These solutions reflect TSMC's different choices for interconnection structures. Although they are not changes in the packaging substrate material itself, they directly affect the connection mode between the interposer and the packaging substrate, and make the substrate need to adapt to different packaging sizes, interconnection densities and manufacturing requirements.
Intel: Exploring Glass Substrates Based on EMIB
Intel focuses on the silicon bridge route, and EMIB is its core solution that has been promoted for a long time. This technology embeds the silicon bridge inside the packaging substrate to provide high-density interconnection for adjacent chips, without spreading silicon interposers over the entire packaging area. This design can reduce the dependence on large-area silicon interposers, reduce the usage of silicon materials, and provide more flexible interconnection methods for different chip combinations.
On this basis, Intel is exploring the combination of EMIB and glass substrates. In early 2026, Intel demonstrated a glass substrate packaging sample based on EMIB, reflecting the technical direction of combining silicon bridge interconnection structures with glass materials. In July of the same year, Intel announced a cooperation plan with precision glass processing enterprise Lens Technology: the two sides will rely on Intel's advanced packaging technology and the partner's glass processing capabilities to explore glass substrate packaging solutions for AI and data center applications.
For Intel, this layout is not simply replacing existing substrates with glass, but trying to combine the dimensional stability of glass materials with the local high-density interconnection of EMIB to provide a new choice for larger-size packaging.
ASE: Expanding Interconnection Structures with RDL and Silicon Bridges
The connection mode between substrates and chips is also changing in the packaging and testing segment. As a packaging and testing enterprise, ASE does not take traditional IC packaging substrate manufacturing as its main business, but reorganizes the interconnection between chips through fan-out packaging and RDL, and then combines with BGA substrates to form the FOCoS solution.
ASE chooses to base on its good fan-out packaging technology, realize the connection between chips through RDL, and then flip-chip mount the entire fan-out package on a high-pin-count BGA substrate. Around different chip combinations and interconnection requirements, the company has further developed solutions such as FOCoS-CF, FOCoS-CL and FOCoS-Bridge.
For the substrate industry, the significance of FOCoS lies in the fact that packaging manufacturers are redistributing the functions of high-density interconnection through RDL and silicon bridges, thereby changing the connection tasks and performance requirements undertaken by packaging substrates. This also shows that competition in substrate-related technologies does not only occur in the substrate manufacturing segment, and packaging enterprises are also participating in the redesign of interconnection structures.
Japanese Enterprises: Promoting Development Around TGV and Next-generation Substrates
On the main line of glass core substrates, Japanese material and printing enterprises are also actively investing.
DNP announced in December 2025 that it will phase in the TGV glass core substrate pilot production line at its Kuki Plant in Saitama Prefecture, and plans to provide samples from the beginning of 2026. The announced sample size is 510×515mm, including two structures of copper-filled type and via wall copper-clad type, and the company plans to establish the production system required for mass production in 2028.
As another printing giant, TOPPAN has a wider layout, covering glass core substrates, glass interposers and organic RDL solutions at the same time. According to its official materials, the company has developed glass substrates with TGV and cavities of different depths, and is exploring next-generation packaging structures combined with FC-BGA substrates.
From the layout of these enterprises, we can see that different levels of changes are emerging in the substrate industry. Substrate competition is no longer limited to a single manufacturing link, but a systematic competition extending from packaging design to material development and manufacturing processes.
Substrate Interconnection: Competition Extends to the Design End
The more complex the packaging architecture is, the more problems need to be handled in the design stage. After GPUs, ASICs and HBMs are integrated, chip layout, interconnection paths, power supply and thermal distribution interact with each other. Different substrate solutions have differences in material properties, circuit structures and manufacturing constraints, so designers need to evaluate signal integrity, power integrity, thermal distribution and mechanical stress in advance.
Therefore, substrates have moved from a supporting link after packaging design is completed to the collaborative design of chips, packages and systems. Enterprises such as Cadence, Synopsys and Siemens EDA are supporting different packaging architectures through design planning, automatic routing, interconnection analysis and simulation tools.
The three EDA manufacturers have different entry angles. Cadence supports multi-chip packaging and substrate interconnection design through Allegro X APD, adapting to various physical structures such as organic substrates and RDL redistribution; tools such as Sigrity and Clarity are used for signal integrity, power integrity and 3D electromagnetic analysis, helping engineers evaluate the impact of different packaging structures and interconnection materials on signal transmission and power supply performance.
Synopsys focuses more on system-level integration, integrating multi-chip system planning, packaging design and verification through 3DIC Compiler, supporting chip partitioning, layout planning and high-speed interconnection routing in 2.5D and 3D packaging, and can handle complex topologies of hybrid architectures of silicon interposers and silicon bridges. This platform also integrates Synopsys' multi-physics field analysis capabilities, and can carry out signal integrity, power integrity, thermal analysis and mechanical stress analysis with relevant tools.
Siemens EDA's Xpedition series covers multi-chip system planning, packaging substrate physical design and verification, and supports different structures such as silicon, glass and organic interposers. Among them, Xpedition Substrate Integrator is mainly responsible for system-level planning and data integration of multi-chips, substrates and interposers, Xpedition Package Designer is responsible for packaging physical design, and Calibre 3DSTACK is used for system-level connection verification.
As the number of chips inside the package and the interconnection density increase, the role of design tools is not only to complete circuit connections, but also to help customers verify the performance and manufacturability of different architectures before manufacturing. For glass core substrates, silicon bridges and large-size RDL structures, design tools also need to adapt to new material parameters, circuit rules and process constraints.
Apart from Materials, Equipment and Testing Are Also Critical
The final implementation of various substrate interconnection solutions depends on material properties, processing accuracy and manufacturing stability. Interconnection architectures such as silicon interposers, silicon bridges and RDLs all have their own manufacturing difficulties. As an emerging route, glass core substrates have material properties that are vastly different from mature organic substrates, so they cannot directly use the entire production line for organic substrates, forming obvious divergences in processing equipment, testing objects and defect types.
For glass core substrates, TGVs need to be formed first, and then electrical connections between upper and lower layers are realized through metallization and copper filling. Glass has good flatness, rigidity and dimensional stability, but its brittleness also increases processing difficulty. TGV processing needs to control the aperture, via wall quality and micro-cracks, and subsequent metallization, circuit construction and dicing also require stricter process control.
In the equipment segment, LPKF is a glass processing equipment supplier that has attracted much attention. Its LIDE (Laser-Induced Deep Etching) technology first performs local modification on glass through laser, and then combines selective wet etching to form structures such as TGVs, instead of simply burning through vias directly with laser. LPKF claims that its NEXAR LIDE equipment can process glass panels with a maximum size of 515×510mm, and the minimum feature size can reach 5 microns.
Glass dicing is also an important link. Edge chipping and micro-cracks generated during processing may affect the reliability of the substrate, so dicing equipment needs to balance accuracy and edge damage control. Testing equipment is related to whether products can be mass-produced stably: if defects cannot be detected in time, the reliability of the entire package may be affected.
In response to these risks, Onto Innovation and KLA have both launched advanced packaging testing and metrology platforms for glass, which are compatible with both organic substrate and glass substrate testing scenarios.
The solution disclosed by Onto Innovation in April 2026 covers full-process online monitoring from TGV preparation to build-up RDL, supports panel testing up to 650×650mm, and can identify items such as via defects, micro-cracks, RDL pattern anomalies, bump height and panel warpage.
The Lumina inspection and metrology system launched by KLA is designed for advanced IC substrate manufacturing, covering glass core substrates and panel-level interposers, and can be used for defect inspection and manufacturing process metrology.
These solutions move quality control from final inspection to the manufacturing process, helping to detect defects in different processes in time. For glass substrates, establishing a testing system running through the entire manufacturing process is the key to improving product consistency and mass production stability. Therefore, the opportunities brought by glass substrates are not limited to substrate manufacturers. Segments including glass processing, laser equipment, wet etching, RDL patterning, dicing and testing may all gain new market space as industrialization advances.
Conclusion
As chip dimensions, interconnection density and packaging forms continue to evolve, the collaboration between substrate manufacturers, material suppliers, equipment enterprises and packaging houses will become closer, and customer verification and supply chain supporting will also become important thresholds for technology implementation.
From the perspective of the industrial chain, future substrate competition will not be a simple scenario where one material replaces another, but will be jointly determined by packaging architecture, design tools, materials, equipment and manufacturing capabilities. Whoever can translate technical advantages into stable mass production will have the opportunity to take a leading position in the next round of advanced packaging competition.