Ex-Intel veterans team up to take on NVLink
Nowadays, as the competition for AI computing power rapidly expands from single-chip performance to cluster interconnection, the high-speed interconnection field has witnessed rare and drastic turbulence.
Two entrepreneurial teams originating from Intel's former networking business have rushed to the most valuable Scale-up interconnection track in the AI era at the same time, directly targeting NVIDIA's core territory. On the other side, the "anti-NVLink Alliance" formed by 115 industry giants is accelerating its assembly, trying to break the monopoly of a single vendor; while NVIDIA has taken the opportunity to play the hidden card of "NVLink Fusion", attempting to replicate the legendary success of CUDA at the hardware layer.
A full-scale hardware showdown that determines the dominance of the next-generation AI data center has officially broken out.
Two former Intel teams rush to the same battlefield
First, let's take a look at Cornelis, a company that has deep ties with Intel. In 2020, Intel spun off its Omni-Path Architecture (OPA) high-performance interconnection business, and the core team founded Cornelis Networks. Lisa Spelman, CEO of Cornelis, worked at Intel for about 20 years before. Up to now, Cornelis still clearly describes itself as "spun off from Intel's high-performance interconnection business", and its technical route is directly inherited from Omni-Path. Omni-Path was originally an important weapon for Intel to challenge Mellanox InfiniBand back then.
However, with Intel's strategic adjustment, this business was eventually divested. In the following years, Cornelis has been developing its high-speed interconnection products around HPC and AI clusters. The currently mass-produced CN5000 still mainly solves the Scale-out problem, that is, large-scale connections between servers and computing nodes. Its switches provide 48 400Gb/s ports, and Director-level devices can provide up to 576 400Gb/s ports.
But after this financing on September 14, Cornelis has clearly crossed a boundary. It officially announced for the first time to enter the Scale-up track.
The so-called Scale-out refers to connecting more servers together; Scale-up is closer to the GPU itself, which requires dozens or even hundreds of AI accelerators in one rack to work collaboratively like a single computer. This is exactly the field where NVLink has long held a dominant position.
On September 14, Cornelis announced a $205 million financing and launched the Active Compute Fabric, an open network architecture integrating programmable computing and cross-scale horizontal and vertical expansion, marking its official entry into the vertically scalable network field. What Cornelis aims to achieve is to enable the network itself to perform computing: this architecture integrates lossless transmission, in-network acceleration and programmable computing. It can directly process data when data flows, offload collective communication and adapt to the evolution of AI algorithms, preventing GPUs from pausing due to waiting for data, and greatly improving accelerator utilization.
Cornelis claims that in a cluster of 100,000 GPUs, traditional networks will lead to about 50% of computing power idling due to data waiting, wasting nearly $1.68 billion and 500 GWh of electricity per year (enough for nearly 48,000 American households). Active Compute Fabric solves this pain point through in-network computing, and is compatible with open standards such as UALink, ESUN and Ultra Ethernet, as well as mainstream accelerators.
Almost at the same time, Delos Data, another startup with Intel background, also announced its financing news.
Ed Doe, CEO and co-founder of Delos Data, also comes from the Intel system. This is a new company founded in 2025 by Ed Doe and Dan Daly. Ed Doe used to be the COO of Barefoot Networks. After Intel acquired Barefoot in 2019, he successively took charge of Intel's Barefoot Division, Intel Switch & Fabric Group and other businesses. Dan Daly is also a veteran of Intel, who has long held senior engineering positions in Intel's networking sector. Reuters defines Delos as a company founded by "Intel veterans".
Delos announced a financing of more than $100 million on September 15, with investors including Matrix, Playground Global, Capricorn, Matter Venture Partners, etc. It is worth mentioning that Playground Global, where former Intel CEO Pat Gelsinger currently works, also participated in this round.
Delos proposed the concept of MoXI (Mixture of X Infrastructure), which refers to the "mixed everything" infrastructure. The Nonstop AI Data Interface it is developing essentially aims to add a unified data interface between these heterogeneous devices and networks. For example, its I/O Chiplet plan for GPUs, XPUs and AI accelerators is designed to be co-packaged directly with computing chips, which can provide multi-protocol I/O bandwidth of over 30Tb/s; in addition, there is a near-packaged optical version of over 10Tb/s, as well as a board-level version of over 400Gb/s for CPUs, flash memory and memory.
Source: Delos
Delos is not a simple substitute for NVLink. Its ambition is even greater: if various GPUs, XPUs, memory and storage can be freely combined through a unified data interface, then the underlying protocol, no matter NVLink, UALink or others, should no longer determine the entire system architecture.
115 companies
formed an "anti-NVLink Alliance"
If Cornelis and Delos are still the offensive moves of startups, then UALink (Ultra Accelerator Link) is the real force that can counterbalance NVLink from the industrial level.
UALink was initially jointly promoted by AMD, Intel, Google, Meta, Microsoft and other companies, aiming to establish an open AI Scale-up interconnection standard. By the end of 2025, the number of members of the UALink Consortium had exceeded 115. Today, the UALink board of directors includes not only AMD and Intel, but also Google, Meta, Microsoft, AWS, Apple, Alibaba, Cisco, HPE, Astera Labs, Synopsys and other companies. It can be said that the members of UALink basically cover the world's most important cloud computing companies, AI chip companies and infrastructure vendors today.
UALink 1.0 supports 200G/lane and can connect up to 1024 AI accelerators in one AI Pod; the new batch of specifications released in April 2026 added capabilities such as In-Network Compute, Chiplet and centralized management. In early September, UALink further disclosed its next-phase roadmap, clearly promoting 400G, optical interconnection, end-to-end reliability and richer management functions.
For these vendors, they do not want all AI computing chips in the future to have to pass through NVIDIA's toll booth. If they have independently developed chips, but the core interconnection inside the rack still has to rely on NVLink, then this "de-NVIDIAization" is obviously incomplete. This is the core business logic of UALink.
NVIDIA's brilliant countermove: NVLink Fusion
NVIDIA has also noticed this. So in May 2025, a very critical change took place. NVIDIA launched NVLink Fusion, a new type of chip that enables all industries to use NVIDIA's NVLink to build semi-custom AI infrastructure.
Before 2025, NVLink was largely a private high-speed interconnection between NVIDIA's internal GPUs. For the first time, NVLink Fusion systematically opens up to third-party CPUs and AI ASICs. The first batch of announced partners includes MediaTek, Marvell, Alchip, Astera Labs, Synopsys and Cadence; Fujitsu and Qualcomm plan to develop CPUs that can form a system with NVIDIA GPUs through NVLink.
Then this list continued to expand rapidly. In November 2025, Arm announced that Neoverse would integrate NVLink Fusion. In December 2025, AWS announced that Trainium4 would integrate NVLink Fusion. In January 2026, the addition of SiFive means that RISC-V CPUs can also access NVLink. NVLink Fusion has connected the three major CPU architectures of Arm, x86 and RISC-V in a very short period of time.
In March 2026, as one of the first batch of NVLink Fusion partners, Marvell further upgraded the cooperation, and NVIDIA also invested $2 billion in Marvell. Marvell will provide Custom XPU, NVLink Fusion compatible Scale-up network, and silicon photonics technology, while NVIDIA will continue to provide NVLink, Vera, ConnectX, BlueField, Spectrum-X and other products.
What is more dramatic is that even NVIDIA's competitors have chosen to "join the camp".
On September 10, 2026, d-Matrix, an AI inference chip company that is one of the typical challengers of NVIDIA, announced that it would join NVIDIA's NVLink Fusion ecosystem. According to the plans announced by both parties, d-Matrix's next-generation Raptor XPU will be directly connected to NVIDIA's rack-level infrastructure, forming a complete system together with Vera CPU, NVLink Switch, BlueField-4 DPU, ConnectX-9 SuperNIC and Spectrum-X Ethernet. The first batch of related systems is expected to be deployed from 2027. In 2025, d-Matrix completed a $450 million financing with a valuation of $2 billion.
Why would a chip company that tries to seize the AI computing market from NVIDIA take the initiative to access NVIDIA's NVLink?
Because NVLink Fusion offers too many benefits: mature Scale-up network that does not need to be redeveloped; mature racks with large-scale deployment of MGX; mature supply chain, with mature suppliers for power supply, liquid cooling, motherboards, switches and chassis; mature data center deployment systems that customers are already very familiar with; more importantly, a shorter time to market, which is particularly critical for startups.
Therefore, the author has summarized that NVIDIA's clearly listed NVLink Fusion ecosystem currently includes: (1) CPU camp: Arm, Intel, Fujitsu, SiFive; (2) ASIC / Custom Silicon camp: Alchip, Astera Labs, GUC, Marvell, MediaTek, Samsung, AWS, d-Matrix; (3) EDA/IP field: Cadence, Synopsys; (4) Optical interconnection camp: Ayar Labs, Lightmatter, Marvell.
From the list of NVLink Fusion, we can also see a phenomenon that many of these vendors are also members of UALink. So the real industrial state is that chip companies are "betting on both sides", which is very similar to the history of PCIe, CXL and Ethernet. On the one hand, they participate in UALink to help build an open alternative ecosystem for NVLink; on the other hand, they actively support NVLink Fusion.
For these companies, the most dangerous thing is not supporting two standards at the same time, but betting on the wrong standard. Especially for interface IP, switching chips, optical interconnection and EDA vendors, the most reasonable business choice is: NVLink AND UALink, rather than NVLink OR UALink.
From a comprehensive perspective, the competition between UALink and NVLink is no longer a simple competition between openness and closedness. At present, NVIDIA has a huge first-mover advantage with six generations of evolution and deep optimization from chips to software; while UALink has responses from hundreds of vendors, its large-scale commercial deployment still needs to wait for the window period of 2026-2027.
In the short term, this battle is not about one side eliminating the other immediately. What really needs attention is whether UALink can turn "openness" into a truly deployable multi-vendor ecosystem; and whether NVLink Fusion can take this window of opportunity to absorb more and more third-party CPUs, ASICs and even competitors into its own rack system in advance.
CUDA locks up the software ecosystem
NVLink locks up the hardware infrastructure
Over the past two decades, many people have believed that as long as a GPU with performance close to NVIDIA's is developed, there is a chance to challenge NVIDIA. Later, people found that things are not so simple. Because what customers use is not just a GPU. They have built CUDA, cuDNN, NCCL, TensorRT, as well as a large number of optimizations, development tools and engineering experience behind PyTorch, all on NVIDIA's software ecosystem.
Therefore, what competitors really need to migrate is not a single chip, but an entire software world. This is the most powerful part of CUDA.
Today, a similar thing is happening again at the hardware infrastructure layer. In the past, an AI chip company only needed to consider whether the performance of its chip was higher than that of the GPU, but now it needs to think about whose rack its chip will be installed in. Because the competition unit of AI systems is upgrading from Chip to System, and then from System to Rack or even the entire AI Factory.
NVIDIA itself is very clear about this. NVLink 6 is no longer an independent GPU interface, but deeply cooperates with software and hardware such as Vera CPU, NVLink Switch, ConnectX, BlueField, Spectrum-X, NCCL and Dynamo. NVIDIA calls this model treating the entire data center as one computing unit.
For NVIDIA, blocking is worse than dredging. Instead of trying to prevent all customers from developing their own chips, it is better to change the gameplay: your chip does not have to be mine, but it can be connected to my platform. Through NVLink Fusion, NVIDIA successfully decouples "chip share" from "platform share". Even if third-party ASICs take away part of the computing power demand in the future, as long as they still run on NVLink, MGX racks and Spectrum-X networks, NVIDIA will still firmly occupy the position of the tax collector of AI infrastructure.
More than a decade ago, CUDA made the industry gradually realize that the most powerful part of a GPU is not just the GPU itself. Today, NVLink Fusion is trying to make the industry face a similar problem again: what is hardest to replace in NVIDIA may no longer just be the GPU, but the entire set of infrastructure around the GPU.
CUDA locks the software ecosystem. Now, NVLink is extending to the hardware infrastructure. It has to be said that NVIDIA has played another brilliant move.