Alibaba Cloud and Tencent have both invested. A Shanghai-based "little giant" chip enterprise is sprinting for the Sci-Tech Innovation Board, with shares held by the second phase of the National Integrated Circuit Industry Investment Fund and plans to raise 3 billion yuan.

According to a report by Xin Dongxi on July 1st, yesterday, Jiyiwei Semiconductor (Shanghai) Co., Ltd. (hereinafter referred to as "Jiyiwei"), a provider of high-speed interconnection solutions, had its application for an initial public offering (IPO) on the Science and Technology Innovation Board accepted by the Shanghai Stock Exchange.

Jiyiwei was established on August 22, 2019, with its registered address in Shanghai. It is a national-level key specialized and sophisticated "little giant" enterprise.

Before the IPO issuance, China Mobile Chain Leader Fund, National Artificial Intelligence Fund, and Second-phase Big Fund held 6.3%, 4.4%, and 1.41% of Jiyiwei's shares respectively. Alibaba Cloud Computing and Tencent Venture Capital held 3.96% and 2.41% of the company's shares respectively.

Jiyiwei adopts a fabless business model and is mainly engaged in the research, development, design, and sales of high-speed interconnection chips, IPs, and related customized application-specific chips. The production process is outsourced to leading wafer foundries, packaging and testing vendors, and other suppliers in the industry.

The company's main products have effectively reduced China's dependence on imported products for high-speed interconnection chips and high-speed interconnection core IPs, and have formed an independent technology solution from core interconnection IPs to various types of interconnection chips.

In 2025, Jiyiwei launched a 224G SerDes IP that meets international advanced rates and achieved IP licensing. In the same year, the company ranked first among domestic manufacturers in the domestic market share of high-speed SerDes IPs with a single-channel rate of 56G and above. Its industrialization process is at the leading level in China and is at the forefront of the industry competing directly with international giants.

During the reporting period, the company's high-speed interconnection SerDes IP products have provided IP licensing services to many leading enterprises in the domestic AI data center industry and XPU industry, and have provided core connection technology support for AI intelligent computing chips, network switching chips, etc.

Jiyiwei uses its self-developed core IP as the technical foundation to complete the independent research, development, and mass production of multiple chips, including high-speed optical digital signal processing oDSP chips suitable for 400G/800G optical modules and board-level relay Retimer chips supporting 400G/800G Ethernet transmission. Both products have been industrialized.

The company plans to raise 3 billion yuan in this IPO. Among them, 1.117 billion yuan will be invested in the research, development, and industrialization project of high-speed interconnection communication chips for the AI and data center fields. 806 million yuan will be invested in the research, development, and industrialization project of multi-scenario ASIC chips based on high-speed interconnection and data conversion core IPs. 645 million yuan will be used for cutting-edge technology research and development projects, and 433 million yuan will be used to replenish working capital.

01. Revenue exceeded 700 million yuan in three years, and the gross profit margins of high-speed interconnection IP and licensing business both exceeded 90%

In 2023, 2024, and 2025, Jiyiwei's revenues were 16 million yuan, 310 million yuan, and 389 million yuan respectively, a growth of about 2256% in two years. The total revenue in three years exceeded 700 million yuan. The net profits were -127 million yuan, -36 million yuan, and 13 million yuan respectively, turning losses into profits. The R & D expenses were 128 million yuan, 184 million yuan, and 156 million yuan respectively.

Changes in Jiyiwei's revenue, net profit, and R & D expenses (Charted by Xin Dongxi)

During the reporting period, Jiyiwei's main business revenue consisted of high-speed interconnection chip business, customized application-specific chip business, high-speed interconnection IP licensing business, and NRE (Non-Recurring Engineering) and other businesses.

During the same period, the company's main business revenue mainly came from the chip sales business (including high-speed interconnection chips and customized application-specific chips). The main chip sales revenues during the reporting period were 2 million yuan, 235 million yuan, and 277 million yuan respectively, accounting for 13.93%, 76.01%, and 71.37% respectively.

The growth of the company's main chip sales revenue was due to the mass production of multiple chips such as high-speed relay Retimer chips and customized application-specific chips and the rapid increase in downstream demand.

During the reporting period, Jiyiwei's revenues from high-speed interconnection IP licensing were 3 million yuan, 74 million yuan, and 85 million yuan respectively, accounting for 18.75%, 23.99%, and 21.76% respectively.

During the reporting period, Jiyiwei's main business revenue all came from the Chinese mainland, and there was no revenue from overseas regions.

During the reporting period, Jiyiwei's gross profit margins for the main business were 12.94%, 48.97%, and 42.4% respectively.

Among them, the gross profit margins of high-speed relay Retimer chips were 41.18%, 17.22%, and 25.9% respectively; the gross profit margins of customized application-specific chips were 55.24%, 54.58%, and 39% respectively; the gross profit margins of high-speed interconnection IP licensing were 99.89%, 90.44%, and 90.63% respectively, which were the highest in the same period.

In 2023, the high-speed relay Retimer chips were still in the customer introduction and risk mass production stages, and the selling price of small batch test chips was relatively high, resulting in a relatively high gross profit margin. In 2024, this type of chips entered large-scale mass production, the unit cost increased, the average price decreased, and the gross profit margin decreased accordingly. After the mass production of customized application-specific chips, the cost decreased due to the scale effect, but in 2025, the company gave corresponding price discounts to key major customers, and the gross profit margin declined.

During each period of the reporting period, the company's gross profit margin for high-speed interconnection IP licensing continued to maintain a high level, mainly because the company maintained strong market competitiveness in the process of continuously enriching relevant product types, expanding applications, and customers. At the same time, this type of business is the licensing of self-developed core IPs, and the relevant costs are relatively low, so the gross profit margin is relatively high.

The changes in Jiyiwei's gross profit margin for the main business are as follows:

During the reporting period, except for 2023 when Jiyiwei's sales scale was relatively small, resulting in a relatively low gross profit margin, the company's comprehensive gross profit margin was generally at the same level as that of comparable domestic companies in the same industry and lower than the average of comparable overseas companies in the same industry.

02. R & D personnel account for up to 75%, and the main products feature high speed and low bit error rate

Jiyiwei's main products feature high speed, low bit error rate, high reliability, high adaptability, and high flexibility. They are widely used in fields such as AI, data centers, network telecommunications, and wireless base stations. The specific situation of the relevant products is as follows:

The high-speed relay Retimer chip is a key signal enhancement component in the high-speed Ethernet transmission link. Its core functions include solving the problems of attenuation and distortion during the long-distance transmission of high-speed signals. The representative composition architecture of Jiyiwei's self-developed single-channel 56G high-speed relay Retimer chip supporting 400G/800G Ethernet data transmission is as follows:

The high-speed optical module is the core device in the optical communication system that realizes the conversion and transmission of optical and electrical signals. Its internal structure can be divided into two core parts: the optical chip group and the electrical chip group. The high-speed optical digital signal processing oDSP chip is the core component of the high-speed optical module.

As the core hub of the electrical chip group, the high-speed optical digital signal processing oDSP chip is mainly used to solve various signal damage problems such as signal attenuation and distortion during the photoelectric/electro - optical conversion and optical transmission processes. The representative composition architecture of Jiyiwei's self-developed single-channel 112G high-speed optical digital signal processing oDSP chip applied to 400G/800G high-speed optical modules is as follows:

Jiyiwei's self-developed customized application-specific ASIC chips are designed according to the specific requirements of users and the needs of specific electronic systems. During the reporting period, based on relevant core technologies such as SerDes, the company provided customers with multiple customized ASIC chip solutions. Taking the solution for home terminal gateways as an example, the representative composition architecture of this solution is as follows:

The high-speed interconnection SerDes IP is the core category of semiconductor interface IPs. It is a pre-designed, verified, and reusable high-speed interconnection functional module.

The core principle of SerDes IP is to convert parallel data into high-speed serial signals for transmission, and perform clock and data recovery and serial-to-parallel data conversion of high-speed serial signals at the receiving end. It performs equalization and compensation for various signal damages introduced during the channel transmission process, breaks through the bottleneck of high-speed signal transmission, and realizes efficient data interaction between chips and between chips and external devices.

The representative architecture diagram of Jiyiwei's self-developed DSP-based SerDes IP is as follows: