The 0.2-nanometer era is approaching, and the latest chip roadmap has been released.

Recently, Imec, a nanotechnology research institution headquartered in Belgium, announced an updated development roadmap at its annual technology forum, ITF, this week. The roadmap indicates that chip manufacturers will face severe challenges in the future.

The next stage of development for CMOS transistors (which are used in almost all chips on Earth) will be Complementary Field-Effect Transistors (CFET: complementary FET). Imec predicts that its commercial application will begin around 2033.

As shown in the figure below, the top row shows the "nodes" of the chip, from the current N2 ("2-nanometer node") to around A2 ("2-angstrom node", 2 angstroms = 0.2 nanometers) in 2041. Let me burst your bubble: N2 doesn't actually represent a physical size of 2 nanometers on the chip. It's just an industry marketing gimmick. These numbers stopped reflecting the actual size of transistors years ago. Of course, there are other numbers that do have meaning, which I'll talk about later. The node names represent generational milestones, and each step promises significant improvements in chip density, performance, and energy efficiency. Each node will bring waves of innovation to the world, some of which may include the next "killer product" because that's what chip manufacturers have been aiming for from the start.

Imec's latest roadmap shows that starting from the A7 node around 2033, the structure of transistors will change. Here is a guide to interpreting the roadmap.

A7: The industry calls it the "7-angstrom" process node. It's just a name; there isn't necessarily a structure with an actual length of 7 angstroms in the transistor.

CPP: Contact Poly Pitch refers to the distance from one transistor to another, measured in nanometers.

Cell: Cell height refers to the minimum size of a logic cell, measured in nanometers.

4.5T: The number of parallel interconnections (wiring) that can be accommodated within the minimum logic cell.

0.55NA EUV: EUV lithography technology with a higher numerical aperture (0.55), which means it can print finer features than today's 0.33NA machines.

MP: This is the minimum pitch that EUV can produce, i.e., the distance between two lines.

As is well known, logic design is achieved by using standard logic cells (which can be thought of as the basic building blocks of each gate in a chip), and Contact Poly Pitch (CPP) is the main factor determining the width of a standard cell. Although it consists of several elements, ultimately it refers to the minimum center-to-center distance between transistor gates. The CPP decreases from 48nm in the N2 process to 39nm in the A3 process. This determines the spacing between transistors.

Therefore, cell height refers to the vertical dimension of a standard logic cell. It shrinks from about 132nm in N2 to about 50nm in A3, almost a threefold reduction.

Combining the above two points, we can get the area of the standard cell and then the density.

Metal pitch refers to the minimum center-to-center distance between adjacent metal lines, which decreases from 22nm in N2 to 12 - 16nm in A3. This is another actual physical density indicator, which basically tells you what kind of lithography technology can be used for each node.

Looking ahead, Imec expects another transistor technology transformation, which is more aimed at reducing power consumption rather than integrating more devices on the chip. By 2041, chip manufacturers may replace the main silicon component - the channel region - of transistors with two-dimensional semiconductors. These materials, such as molybdenum disulfide, can exhibit semiconductor properties even when they are only a single atomic layer thick.

Yes, 15 years is indeed a long time in an ever-changing industry like semiconductors. Paul Heremans, the Chief Technology Officer of Imec, said that Imec can make such long-term predictions because its research plays an important role in the semiconductor industry. "Our research projects aim to reduce the risks of technical solutions," he said. That is, they explore the costs and benefits of different solutions to help chip manufacturers narrow down their choices. "We must be well-prepared before these technologies are actually applied to products because even after we complete the risk assessment, a lot of engineering and development work is still needed to put these technologies into production," he added.

With the goal of reducing risks, most of Imec's current efforts are focused on what will happen in 2033, which is CFET.

Too Many Options for CFET

Before talking about CFET specifically, let's share some basic concepts of transistors.

A chip contains billions of transistors, and each transistor has a gate (just like a door!). All these transistors are interconnected (just like roads), and they act as current switches (just like opening a door). The key elements of a transistor include the gate (used to regulate the conductivity in the channel), the source (where the driving current flows into the channel), and the drain (where the current flows out of the channel). Therefore, the role of the gate is basically to control the on and off of the transistor, allowing or blocking the flow of current. This enables the current to access, send, receive, and process digital data, thereby generating instructions and information.

To be an efficient switch, a transistor needs to do three things well: allow as much current as possible to pass through when it is on (driving current), allow as little current as possible to pass through when it is off (preventing leakage), and switch between on and off as quickly as possible (performance). It is these parameters that have driven the innovation and development of transistors over the years.

FinFET (the workhorse in the 2010s and early 2020s): Starting from the 14-nanometer process node, the industry achieved a leap from two-dimensional planar transistors to three-dimensional FinFETs. In a three-dimensional FinFET, the gate no longer only covers the top of the silicon fin but surrounds three sides of the channel. This greatly improves the accuracy of current control, reduces leakage, and lowers the required gate voltage. However, there are limits to the height of the fins and the number of them arranged side by side. Beyond these limits, electromagnetic interference will occur. Today, we have reached this bottleneck.

Nanosheet/Gate-All-Around Field-Effect Transistor (GAAFET): Replacing vertical fins with horizontal nanosheet stacks, voila! The gate now surrounds all four sides of the channel, further reducing leakage and increasing the driving current. Chip manufacturers can also flexibly adjust the width of the nanosheets to better suit specific chip designs: wider nanosheets mean higher driving current, while narrower nanosheets optimize power consumption. This is the most advanced transistor in mass production at present, and Imec expects this architecture to lead the development roadmap for future generations and eventually transition to CFET.

CFET aims to achieve the functions of two transistors in the space of one. For decades, CMOS logic circuits have been driving computers, and they rely on two types of transistors: PMOS and NMOS. Their working principle is that the same input signal will turn one transistor on and the other off, enabling relatively efficient operation. Currently, they are usually installed in pairs side by side. Supporters believe that CFET can stack them, reducing the area of some circuits by half.

A possible way to implement CFET is to manufacture two transistors simultaneously instead of one by one, or to manufacture them on different wafers and then fuse them together. First, multiple alternating layers of silicon and silicon-germanium are deposited on a silicon wafer. After etching trenches and other structures in these layers, an etchant is used to etch the silicon-germanium layers without damaging the silicon layers, forming a stack of suspended silicon ribbons with nanoscale thickness. The top silicon ribbon (called a nanosheet) forms the PMOS transistor, and the bottom silicon ribbon forms the NMOS transistor, or vice versa.

The world's largest chip manufacturers - Intel, Samsung, and TSMC - are currently working on mass-producing CFET-based chips. Each of them has manufactured a CFET chip prototype. TSMC's engineers announced at the IEEE International Electron Devices Meeting in December last year that the company used its devices to manufacture an ultra-compact memory cell and a key test circuit called a ring oscillator. In June this year, at the IEEE Symposium on VLSI Technology and Circuits, Samsung will detail a CFET that is the smallest in size and consists of the most layers of nanosheets (a total of six layers) to date.

However, Heremans pointed out that how to best manufacture CFET is far from settled. "Obviously, there are still many solutions to be explored." For example, Imec has been developing new methods to better electrically isolate the upper and lower transistors so that they can work independently. The process to achieve this is very complex. The silicon and silicon-germanium layers that make up the top transistor will be manufactured on a completely different silicon wafer. Then, the two wafers are bonded together in a specific way so that only the silicon and silicon-germanium layers on the top wafer are connected to the bottom wafer. The process also adds an additional insulating layer between the materials of the top and bottom wafers to provide the required electrical isolation.

From the roadmap, it actually shows three types of CFETs: monolithic CFET (stacked step by step on the same wafer), sequential/bonded CFET (n-type and p-type stacks are built on different wafers and bonded together), and finally, thin-channel two-dimensional material CFET (where the silicon channel is replaced by an atomic-thin layer).

Although this seems difficult, it also helps to solve the problem of the mismatch in charge transfer speed between PMOS and NMOS devices. Current chips use silicon wafers cut along crystal planes that are favorable for NMOS conduction. But if the PMOS layer is manufactured on a separate wafer, the wafer can be cut to be more favorable for PMOS device conduction. Intel is currently testing this solution and will announce the research results at the IEEE Symposium on VLSI Technology and Circuits in June.

Imec expects the development process of CFET to be similar to other recently introduced technologies, such as FinFET 15 years ago and the currently commercialized nanosheet transistors. That is, first, there is an initial product launch, then efforts are made to improve density and performance, and finally, the goal is to further improve performance or energy efficiency in the high-density version.

After that, Imec expects that around 2041, the industry will replace the silicon material in CFET with one or more new two-dimensional semiconductor materials. Different from the CFET transformation, the main role of two-dimensional semiconductors is to reduce power consumption.

"The overall goal of advancing the roadmap is, of course, to propose technologies that can improve the power generation efficiency per watt," Heremans said. In advanced chips, a small reduction in voltage can significantly reduce power consumption.

This is where the advantage of two-dimensional semiconductor technology lies. Heremans pointed out that the thickness of two-dimensional semiconductors is less than one nanometer, while the thickness of future silicon nanosheets will be three nanometers. Therefore, compared with thicker silicon nanosheets, the transistor gate surrounding the channel region only needs a lower voltage to control the current flowing through such a thin structure. Heremans also said that if the industry chooses a semiconductor material with a faster charge flow speed, the efficiency of two-dimensional CFET is expected to be further improved.

Interconnects, Packaging, Lithography, etc.

If CFET arrives as Imec predicts, it will enter an industry that already has a three-dimensional mindset. Intel has moved the power supply interconnects below the silicon transistor layer on the chip, and given the complex connection methods of CFET, some data signals may also need to be moved here.

Equally important, by 2033, chip companies will have more than a decade of experience in chip stacking, increasing the total amount of silicon in the processor. For example, in AMD's MI300 GPU, the "compute units" manufactured using the most advanced process are stacked on another chip manufactured using an older process, which is responsible for handling the GPU's memory and communication functions.

The vertical connection pitch in AMD chips can be as small as 9 microns, and this pitch is shrinking rapidly. "The most advanced wafer bonding technology we are currently developing can achieve a pitch of about 200 nanometers," Heremans said. "This means that within one square millimeter, we can achieve 25 million interconnects."

This density means that designers can start building logic circuits on 3D chips," Heremans said. This ability will lead to innovation in the field of chip design, which Imec calls CMOS 2.0. In this solution, not only can multiple chips manufactured using different technologies be stacked together, but also a single chip can be manufactured by fusing multiple layers of transistors, with each layer of transistors optimized for specific functions, such as storage density or driving current. "This will greatly improve the performance of this integrated chip," he said.

It should be emphasized that CMOS 2.0 is the name Imec gives to the development paradigm after 2030. In this paradigm, the system-on-chip is no longer a single monolithic chip but multiple functional layers stacked vertically, with each layer using the technology most suitable for itself. High-density logic uses the most advanced process nodes, caches use process nodes optimized for density and cost, and I/O and power management use another process node. All components are connected into a complete system. The key is that not every part of the chip needs to use the most advanced process node. CMOS 2.0 reserves the most advanced (and most expensive) process for high-density logic that truly benefits from it and divides all other components into layers built using corresponding processes. The roadmap reflects this through cell height markings (such as "5.5T over 5.5T") and marks the wafer bonding pitch in the middle.

In the roadmap, there is also a part that is most easily underestimated and is one of the most important innovations in the current chip manufacturing field.

Today's chips use the front-side power supply method ("front-end power supply"), which means that the power lines need to pass through multiple layers of metal wiring to reach the transistors at the bottom of the chip. This not only takes up valuable chip space but also causes power loss during the process of passing through multiple layers of metal wiring. In some advanced chips, the power may even need to pass through 15 or more metal layers to reach the transistors.

The "backside power supply" technology overturns the traditional power supply method by supplying power from the bottom (or "backside") of the chip and more directly contacting the transistors through Through-Silicon Vias (TSV). In this way, the "front-side" space can be used to increase the transistor density, while improving the overall power consumption and performance of the chip. In addition, it also simplifies the bonding between wafers on the top of the chip, which is crucial for achieving 3D chip stacking.

The roadmap shows two stages. First, it is the backside power supply for global interconnects (the current generation, to be launched in 2025/2026). Then, starting from A14, the backside signal wiring will be merged with the backside power supply, almost completely freeing up the front-side space for the most density-demanding interconnects. The implementation methods of major chip manufacturers are different: Intel's "PowerVia" connects to the transistor contacts, while TSMC's "Super Power Rail" (just the name sounds great!) connects directly to the source and drain. Although it is more difficult to manufacture, it can bring greater expansion advantages. But that's how any innovation is: if it were easy, everyone would do it. This requires the cooperation of the entire semiconductor manufacturing ecosystem, including deposition, etching, chemical mechanical polishing, bonding, wafer thinning, and other processes.

The bottom row of the new roadmap also shows the possible development directions of these systems. The silicon interposer among them is becoming an active layer.

Today's AI accelerators are located on a passive silicon interposer (an electrical interface layer), which is mainly used to transmit signals between the computing chip and the memory stack. The roadmap shows that with the advancement of each node technology, this technology is also developing steadily. Starting from the A14 node, the interposer will integrate "IGZO" transistors (indium gallium zinc oxide, a thin-film