Wafer foundry, competing for 1nm
As the drums of the 2nm process have just sounded, the semiconductor industry's attention has already turned to the more cutting - edge technological uncharted territory - the 1nm (A10) node. This is not only the ultimate test ground for Moore's Law but also the watershed for the chip manufacturing process to move from the "nanometer era" to the "angstrom era."
According to the roadmap for sub - 1nm process nodes of future silicon - based transistors released by IMEC (Interuniversity Microelectronics Centre), by 2036, semiconductor devices will enter the atomic (angstrom) era from the nanometer era. This means that the atomic - level precise manufacturing of silicon materials will become the strategic breakthrough direction for the development of semiconductor technology. One nanometer is equal to 10 angstroms, which means that humans will build transistors at the atomic scale, and the position of each atom is crucial to success or failure.
The three major industry giants, TSMC, Samsung, and Intel, have all disclosed plans related to the 1nm - level process, pushing this arms race in advanced processes into the angstrom era. At this node, the transistor architecture will evolve from GAA nanosheets to CFET (Complementary Field - Effect Transistor). The lithography machine needs to achieve a numerical aperture of 0.55 or even 0.75, and the cost of the wafer fab will soar to over $30 billion. This is a high - stakes gamble that only top players can participate in.
Continuous News of 1nm Mass Production
In terms of mass - production progress, the timetables of several giants are both in pursuit of each other and have their own reservations.
As the global leader in wafer foundry, TSMC has captured nearly 70% of the global wafer foundry market and has long led the industry in the field of advanced processes. Currently, its 2nm N2 process will achieve mass production by the end of 2025, and this year it will see large - scale commercial use by leading customers such as Apple and AMD. The subsequent A16 process will be first used in NVIDIA's Feynman GPU, with trial production starting at the end of the year and official mass production in 2027.
In the more cutting - edge 1nm race, TSMC's layout has already been implemented. According to the plan, its first angstrom - level process A10 (1nm) will be officially launched in 2030. By then, the number of transistors in chips using TSMC's 3D packaging technology will exceed 1 trillion, and even for chips with traditional packaging, the transistor scale will exceed 200 billion. In terms of production capacity support, the Tainan Salun Park with a total area of 531 hectares will enter the second - phase environmental assessment in April this year and complete the final environmental assessment in the third quarter of 2027. According to TSMC's previously announced plan, the park is planned to build 6 wafer fabs. Among them, factories P1 - P3 will focus on the 1.4nm process A14, and factories P4 - P6 are specifically designed for the 1nm process A10. There is no ruling out the possibility of a 0.7nm process in the later stage. In addition, there are reports that TSMC's planned Tainan Fab 25 can accommodate 6 production lines, also laid out according to the specifications of P1 - P3 lines for 1.4nm and P4 - P6 lines for 1nm. Before A10, TSMC is expected to launch the 1.4nm process A14 in 2028, upgrading the second - generation GAA transistor structure and back - side power supply technology.
Samsung Electronics has set the goal of completing the development of the 1nm - level advanced process SF1.0 and transferring it to the mass - production stage before 2030, aiming to compete with TSMC for the right to speak in advanced processes.
Behind Samsung's aggressiveness lies an embarrassing real - world dilemma. Although it was the first to release the Exynos 2600 chip using the 2nm process, its trial - production yield was only 30%. It was only at the beginning of this year that the yield of its 2nm GAA process (SF2) increased to 50%. In contrast, TSMC's 2nm process achieved a yield of 60% in the initial stage. More seriously, core customers such as Qualcomm and AMD have continuously shifted their orders to TSMC, and even Samsung's own Galaxy S25 series has abandoned the Exynos chip and switched to Qualcomm's Snapdragon.
Intel updated its roadmap at the 2024 Foundry Direct Connect event: the 14A (1.4nm) node will start production in 2026, and the 10A (1nm) node will enter the development/production stage by the end of 2027.
Japan's Rapidus is also actively deploying. Rapidus was jointly established by eight large Japanese companies including Sony and Toyota, with the ambition to significantly shorten the technology gap with TSMC to within six months. It is currently actively developing 1.4nm technology and will start production in 2029. However, some market analysts predict that Rapidus may try to start operations as early as the end of 2028. This Japanese wafer foundry has shown strong momentum in business promotion, but it still faces severe structural challenges, namely the lack of a large Fabless market in Japan that can absorb the huge demand for 1nm chips.
Analysis of 1nm Technical Strength
The technical challenges of the 1nm process far exceed those of the past, and the core lies in the generational leap of the transistor architecture.
Evolution from GAA to CFET
Currently, the 2nm node generally uses GAA (Gate - All - Around) nanosheet transistors, but the 1nm node requires a more radical architecture. IMEC's roadmap shows that from the 2nm to the A7 (0.7nm) node, the Forksheet design will be adopted, and then CFET (Complementary FET) will be introduced at the A5 and A2 nodes.
Samsung has clearly stated that it will use the Forksheet structure at the 1nm node - an evolved version of the GAA nanosheet. On the basis of the standard GAA, a dielectric wall is added, which can further improve the transistor density and performance. TSMC may not immediately adopt CFET in the 1nm process but will continue to optimize the GAA architecture.
The core breakthrough of CFET lies in 3D vertical stacking: stacking N - type and P - type transistors vertically and sharing the same gate, the area can be reduced by 50%, and the current density can be doubled. This means that on the same chip area, the transistor density will achieve a qualitative leap. However, the CFET architecture requires atomic - level precision in the front - side wafer stacking process, and the alignment of multi - layer devices is extremely difficult, so there are significant challenges in industrial implementation.
It is worth noting that according to the previous technical path, CFET was originally the recognized benchmark for the next - generation architecture. However, the FlipFET technology proposed by Peking University in China has achieved the three - dimensional vertical integration of 8 - layer transistors for the first time, with the logic density per unit area 3.2 times higher than that of traditional FinFET and the power consumption reduced by 58%. This breakthrough result is regarded by the industry as one of the most promising solutions to continue Moore's Law . Different from CFET, which relies on a complex front - side wafer stacking process, FFET first manufactures n - type transistors (such as FinFET NMOS) on the front side of the wafer, and then bonds another wafer, flips and thins it to manufacture p - type transistors (such as FinFET PMOS) on the back side. This structure does not require vertical stacking but achieves spatial separation of n/p devices through physical flipping, fundamentally avoiding the multi - layer alignment problem of CFET.
Extreme Challenges of Lithography Technology
The 1nm process places almost demanding requirements on lithography technology. ASML's High - NA EUV (0.55 NA) lithography machine has been delivered, with its resolution improved to an 8nm line width. In theory, it can support the production of 1nm chips under double exposure. However, each device costs more than 350 million euros, weighs 150,000 kilograms, and requires 250 engineers to spend 6 months for assembly.
Further in the future, ASML is developing the Hyper - NA EUV (0.75 NA), which is expected to be launched around 2030, and the corresponding products will be named the HXE series. ASML predicts that the Hyper AN lithography machine may be able to achieve mass production of 0.2nm or even more advanced processes, but it is not completely certain at present.
Back - Side Power Supply and New Materials
To relieve wiring congestion, the 1nm node will generally use the back - side power delivery network (BSPDN) technology, moving the power transmission network to the back of the transistor, thereby improving signal integrity and reducing power consumption. In addition, research on two - dimensional materials such as molybdenum disulfide (MoS₂) as transistor channel materials is also accelerating. It can still maintain switching characteristics at the 1nm scale, and its electron mobility is 10 times higher than that of silicon.
1nm Market Potential
TSMC predicts that by 2030, the number of transistors in chips using 3D packaging technology will exceed 1 trillion, and the number of transistors in chips using traditional packaging technology will exceed 200 billion. In contrast, the current NVIDIA GH100 only has 80 billion transistors.
What does this mean? The computing power of AI training chips will see a new round of explosion. TSMC points out that each generation of process from 5nm to A14 will achieve about a 30% improvement in power - consumption efficiency, a 15% performance gain, and a 20% increase in transistor density.
Samsung has placed its bet on 1nm on AI chips. According to South Korean media reports, Tesla's AI6 chip will use Samsung's SF2T process for mass production in 2027, and Samsung's 1nm process will target the next - generation AI accelerators.
What is even more noteworthy is that the manufacturing cost of 1nm chips will reach astronomical figures. From 3nm to 2nm, the wafer cost has risen from about $18,000 to $30,000. If this trend continues, the cost of 1nm wafers may reach over $45,000 (about 320,000 RMB) or even higher. This not only tests the financial strength of chip design companies but may also reshape the business model of the entire semiconductor industry.
Hidden Winners
In this global competition for the 1nm process, in addition to the head - on confrontation among wafer foundry giants, the core players in the upstream of the industrial chain have long become the key forces determining the outcome of the battle and even the hidden winners of this competition.
First and foremost is the lithography machine giant ASML. ASML monopolizes the advanced lithography machine market, accounting for 90% of the share. Its EUV and high - numerical - aperture EUV lithography machines are the core equipment for chips with a process of 3nm and below. In the competition for 1nm, ASML remains an irreplaceable key player.
Recently, imec announced that ASML's EXE:5200 high - numerical - aperture EUV lithography system was officially launched, which is the most advanced lithography tool at present. imec expects that the EXE:5200 high - numerical - aperture EUV lithography system will complete full certification in the fourth quarter of 2026. At the same time, the ASML - imec joint high - numerical - aperture EUV lithography laboratory in Veldhoven will continue to operate to ensure the continuity of high - numerical - aperture EUV R & D activities of imec and its ecosystem partners. ASML's EXE:5200 (High - NA EUV) will be the ticket to the 1nm process.
In addition, other process equipment such as etching and thin - film deposition is also of great importance. In March this year, IBM announced a cooperation with semiconductor equipment manufacturer Lam Research on the development of sub - 1nm advanced logic processes. The new five - year agreement between the two sides will focus on the joint development of new materials, advanced etching/deposition processes, and High NA EUV lithography. The two companies will combine IBM's advanced research capabilities at the Albany campus and Lam Research's end - to - end process tools and innovative technologies. The team will build and verify the complete process flow of nanosheet and nanoscale stacked devices and back - side power supply. These capabilities are designed to reliably transfer High NA EUV patterns to actual device layers, achieve high yields, and support continuous miniaturization, performance improvement, and a feasible mass - production path for future logic devices.
Applied Materials also recently announced the launch of two deposition equipment suitable for the angstrom - level process (1 angstrom = 0.1 nanometer). These two pieces of equipment have been introduced into the cutting - edge processes of 2nm and below of leading logic chip manufacturers. Applied Materials said that the GAA all - around gate structure is becoming the inevitable choice for cutting - edge processes, which can bring significant energy - efficiency improvements. However, the GAA structure is more complex than FinFET and requires more than 500 processes for manufacturing, many of which require new material deposition methods.
Generally speaking, the competition for the 1nm process is actually a three - dimensional war of "technology, capital, and patience." TSMC still moves forward steadily, maintaining its lead through customer stickiness and technological accumulation; Samsung tries to overtake on a curve through an aggressive roadmap and architectural innovation (Forksheet); Intel hopes to return to the first echelon in 2027 with the support of the US Chip Act; and Rapidus, as a new player, is trying to find opportunities in the gaps with the strategy of "the fast fish eats the slow fish." Behind all this, the support of semiconductor equipment manufacturers is also needed.
Will 1nm be the end of Moore's Law? Perhaps in 2030, when the first A10 wafer comes off the production line, we will find the answer. But one thing is certain: the battle for "1nm" has quietly begun.
This article is from the WeChat official account "Semiconductor Industry Insights" (ID: ICViews), author: Peng Cheng, published by 36Kr with authorization.