Advancement of NiuXin PCIe IP: From PCIe 3.0 to PCIe 5.0, Strengthening the Foundation of Chip Interconnection

As the "data highway" connecting core components such as CPU, GPU, and NVMe solid-state drives in SoC chips, the performance and stability of the PCI Express (PCIE) interface IP directly determine the communication efficiency of the entire system. In today's era of booming demand for AI, high-performance computing (HPC), and data centers, high-speed and reliable I/O interconnection has become the key to the breakthrough of chips.

Relying on its profound technical accumulation in the field of high-speed interfaces, NiuXin Semiconductor has successfully overcome the core technologies of the entire series from PCIE 3.0 to PCIE 5.0 and formed a complete solution. At present, NiuXin's PCIE IP has been successfully adopted by several well-known domestic chip manufacturers, and some projects have completed tape-out verification.

PCIe 5.0 IP: Breaking through at a rate of 32GT/s to strengthen the computing power foundation

Facing the extreme demand for bandwidth in AI large model training, high-performance computing, and next-generation data centers, PCIe 5.0 has increased the transmission rate to 32GT/s, becoming the key to breaking through the system performance bottleneck. The PCIe 5.0 IP independently developed by NiuXin Semiconductor adopts an advanced analog front-end architecture and digital signal processing algorithms, effectively overcoming the signal loss and noise interference during high-speed transmission, and providing a self-controllable high-speed interconnection solution for high-end chips.

NiuXin Semiconductor's PCIe 5.0 IP has solid underlying technical strength and can meet the strict requirements of high-end chips for high-speed interconnection. This IP integrates a high-performance clock data recovery (CDR) circuit and adopts multi-tap transmitter feed-forward equalization (FFE) and receiver decision feedback equalization (DFE) technologies to construct a complete link equalization solution, which can effectively improve the channel margin and support continuous link equalization, ensuring the stability of data transmission.

Currently, this IP has completed silicon verification based on the mainstream 12nm advanced process node. The insertion loss compensation ability, bit error rate, and various compatibility indicators all meet the protocol standards and have been adopted by leading chip customers. It is being applied in flagship projects such as AI computing power super nodes, data acceleration cards, and high-end SSD controllers, helping to boost the performance of high-end computing power chips.

Figure 1: Eye diagram quality of the PCIE5 PHY transmitter at 32GT/s

PCIe 4.0 IP: Empowering high-performance computing and AI applications

With the increasing demand for data bandwidth in applications such as artificial intelligence, data centers, and enterprise-level storage, PCIe 4.0 has become the mainstream choice for the design of a new generation of high-performance chips. NiuXin Semiconductor's PCIe 4.0 PHY IP solution aims to provide customers with a cost-effective interconnection upgrade path.

This IP adopts the industry-standard PMA/PCS hierarchical architecture, natively supports the PIPE interface, and integrates self-developed low-jitter clock synthesis technology and a complete adaptive equalization solution (FFE + CTLE + DFE). This design significantly improves the signal integrity in complex channel environments and ensures an extremely low bit error rate. Currently, this solution has been verified on the mainstream process platforms of 28nm/22nm and has been adopted by customers, and is about to enter the mass production stage; at the same time, it has also completed development and verification on advanced process nodes such as 12nm. This solution has been adopted by well-known manufacturers and will be applied on a large scale in key projects such as PCIe switch chips and PCIe Retimer re-timers.

Figure 2: Eye diagram quality of the PCIE4 PHY transmitter at 16GT/s

PCIe 3.0 IP: A reliable interconnection solution under mature processes

PCIe 3.0 is still a widely used and cost-effective interface standard in the current market. NiuXin Semiconductor's PCIe 3.0 PHY IP has deeply optimized the chip area and power consumption while ensuring stable performance.

This IP supports transmission rates of 2.5GT/s, 5GT/s, and 8GT/s, integrates an adaptive clock data recovery circuit and an advanced analog front-end architecture, and can achieve intelligent adaptation to diverse channels and temperature tracking. Currently, this IP has completed silicon verification on mainstream mature process nodes such as 22nm/40nm and has been successfully mass-produced in the field of PCIe 3.0 switch chips. With its multi-port configuration and low-latency design, it has become an ideal choice for fields such as data centers, industrial automation, and consumer electronics.

Figure 3: Test results of the internal eye diagram of the PCIE3 PHY receiver at high and low temperatures under long, medium, and short channels

Hardcore technology: In-depth optimization from the physical layer to the subsystem level

NiuXin Semiconductor's PCIE IP solution can provide customers with a one-stop subsystem solution.

1. Excellent signal integrity: Through fine analog front-end design and equalization technology, the bit error rate (BER) of our IP can reach better than the industry standard of 10⁻¹² under various process and channel conditions, ensuring extremely reliable data transmission.

2. Flexible configuration and low power consumption: It supports various channel width configurations such as x1/x2/x4/x8/x16 and can flexibly adapt to different bandwidth requirements. At the same time, the deeply optimized power management strategy enables it to perfectly meet the requirements of power-sensitive mobile and embedded applications.

3. Complete compatibility: Our IP solution is fully compatible with the PCIE 5.0/4.0/3.0/2.0/1.0 standards, ensuring seamless docking with the customer's existing ecosystem.

Facing the future demand for higher-speed data transmission, NiuXin Semiconductor has laid out the next-generation interconnection standard in advance. Currently, NiuXin Semiconductor's PCIe 6.0 IP has completed development and is actively promoting mass production, continuously maintaining the rhythm of technological iteration and making full preparations for future computing power upgrades.

NiuXin Semiconductor has won the trust and recognition of customers through its rapid technical response and in-depth customized service capabilities. In addition to providing mature IP verified by silicon, NiuXin Semiconductor can also provide full-process technical support from link simulation, signal integrity analysis to system-level debugging according to the specific needs of customers, helping customers significantly shorten the product launch cycle.

This article is from the WeChat official account "NiuXin Semiconductor", written by NiuXin Semiconductor, and is published by 36Kr with authorization.