Next-generation storage materials
In recent years, oxide semiconductors have received extensive attention as potential materials for next - generation storage architectures. Their key advantage lies in the ability to realize logic and storage devices compatible with the back - end - of - line (BEOL) interconnect process. This paper reports the recent progress and challenges of BEOL storage devices based on oxide semiconductor channels, including DRAM - like 1T - 1C storage cells, capacitor - less gain cells, and non - volatile ferroelectric field - effect transistors (Ferroelectric FETs). The paper analyzes the key characteristics of oxide channels, focusing on the progress in materials and device process technologies. These advancements contribute to improving the core indicators of memories, such as endurance, data retention characteristics, and scalability. These research results provide valuable references for optimizing storage devices based on oxide semiconductors to meet the requirements of next - generation applications.
Introduction
The rapid popularization of generative artificial intelligence applications (such as large language models, LLMs) has triggered a shift towards a data - centric computing paradigm and put forward unprecedented demands for new storage technologies. These storage technologies must have higher capacity and bandwidth and perform better in terms of energy efficiency to support increasingly complex workloads. To address these challenges, oxide semiconductor (OS) channel materials are becoming important candidates for innovative storage cell designs. These designs aim to complement existing storage solutions (such as SRAM and DRAM) and drive the transformation of the storage system hierarchy by realizing BEOL - compatible storage architectures. Notably, memories based on oxide semiconductors possess unique characteristics, such as the Cell - over - Peripheral (COP) design, thanks to their ability for monolithic integration with advanced CMOS logic devices.
Significant progress has been made in n - type oxide semiconductors, including materials such as IGZO, InWO, InSnO, and InO. Due to their ultra - low leakage characteristics and compatibility with low - temperature budget processes below 400 °C, these materials have become natural choices for BEOL storage cell access transistors. However, finding p - type oxide channel materials with matching performance remains more challenging. This area is still an active research field, and combining it with n - type oxide semiconductors is expected to drive new applications beyond the storage system itself. Table I summarizes three main types of BEOL - compatible memories based on oxide semiconductor channels that are currently being intensively studied:
Table I: Summary of main BEOL - compatible memories based on oxide semiconductor (OS) channels
(1) DRAM - like 1T - 1C storage structure using ultra - low leakage n - type oxide semiconductor access transistors;
(2) Capacitor - less gain cell memories composed of n - type and p - type oxide semiconductor transistors, with structural forms including 2T - 0C or nT - 0C;
(3) Ferroelectric field - effect transistors formed by combining an n - type oxide semiconductor channel with an Hf - based ferroelectric dielectric
In this paper, we will review the latest progress in oxide semiconductor (OS) - based storage cell technologies and discuss the progress and challenges in materials and device development to meet performance requirements. By discussing n - type and p - type oxide channels, we aim to provide references for the key factors affecting device design, scalability, and reliability in emerging storage architectures.
n - type OS transistors for DRAM - like 1T - 1C
Recently, a 1T - 1C storage chip using n - type oxide semiconductor transistors has been demonstrated on an advanced logic platform, showing a high degree of maturity in manufacturing process and foundry compatibility and achieving excellent performance (see Figure 1(a)). The chip achieved a random cycle time of 8 ns and a retention time of 128 ms at a VDD of 0.75 V and exhibited multi - year reliability at 85 °C (see Figure 1(b)). The entire storage cell array is monolithically integrated on top of the CMOS peripheral circuit in a COP structure, providing significant advantages in density expansion, delay reduction, and power consumption reduction by minimizing the signal propagation distance. The extensive research on n - type oxide semiconductor materials and their maturity have played a key role in achieving this breakthrough.
Figure 1: (a) Cross - sectional TEM image of a BEOL 1T - 1C memory using a COP structure; (b) Shmoo plot of the 1T - 1C storage chip, showing a good performance margin.
However, to meet the stringent performance and reliability requirements, several key challenges still need to be addressed: (1) achieving high drive current (ION) through contact resistance (RC) optimization in short - channel (LG < 30 nm) devices to support ultra - low voltage (< 0.75 V) operation and reduce power consumption; (2) threshold voltage (VT) regulation to suppress leakage while maintaining robust circuit functionality; and (3) process and passivation control to reduce VT fluctuations and improve reliability. Figure 2 shows a schematic diagram of strategies for optimizing the performance of n - type OS transistors.
Figure 2: Schematic diagram of strategies for optimizing the performance of n - type OS transistors.
In scaled n - type OS devices, reducing the contact resistance (RC) is crucial for improving ION. Figure 3(a) compares the ID - VG characteristics before and after RC optimization, where the optimization measures include: (1) reducing surface damage caused during contact etching through contact process engineering; (2) reducing the metal/semiconductor Schottky barrier (SB) height through contact interlayer (IL) optimization. By combining these methods, an RC value of less than 500 Ω·μm was achieved (see Figure 3(b)).
Figure 3: (a) Comparison of ID - VG characteristics before and after contact resistance (RC) optimization; (b) RC values extracted by the TLM method, showing that the optimized RC is less than 500 Ω·μm.
Different from silicon - based transistors, fundamentally different methods are required for VT regulation and its fluctuation control in oxide semiconductor - based transistors, which involves precise regulation of the delicate balance between the metal ion concentration, oxygen vacancies, and hydrogen content in the OS channel. Figure 4 shows the wide - range tunability of the VT of OS transistors achieved through precise control of the channel composition. However, such methods often introduce an undesirable trade - off between VT and ION, so continuous research in materials and process optimization is still needed to solve this problem.
Figure 4: Tunability of VT achieved through precise control of the oxide semiconductor (OS) channel composition, revealing a typical trade - off between VT and ION.
The reliability performance (including positive bias temperature instability and negative bias temperature instability, PBTI/NBTI) of OS channel transistors is highly sensitive to the presence of hydrogen. Existing studies have shown that complex PBTI and NBTI behaviors occur in n - type OS systems due to hydrogen diffusion and defect formation. To mitigate these effects, surface treatment and passivation methods have been adopted to minimize the hydrogen content and prevent its diffusion into the channel during the process, as shown in Figure 5.
Figure 5: SIMS depth profile of the OS channel, showing that the hydrogen content in the channel is effectively reduced through surface treatment and passivation.
Figure 6 shows the endurance test results of a 1T - 1C storage chip fabricated using an optimized process flow. After 10¹⁴ cycles at 85 °C, its bit error rate (BER) is still less than 1 ppm. Figure 7 shows the optimized performance of n - type OS devices at 25 °C and the cumulative distribution curves of VT and ION, verifying the robustness of the process with small die - to - die variations across the entire wafer. The performance benchmark results are shown in Table II. At the shortest gate length (LG < 30 nm), the highest ION under positive VT conditions is achieved.
Figure 6: Endurance test results of the 1T - 1C storage chip. After 10¹⁴ cycles at 85 °C, the bit error rate (BER) is still less than 1 ppm.
Figure 7: Cumulative distribution of the threshold voltage (VT) of optimized n - type OS devices on a 300 mm wafer.
p - type OS transistors in 2T - 0C gain cells
The capacitor - less 2T - 0C gain cell (GC), composed of a write transistor and a read transistor, can achieve non - destructive readout and is a promising solution for high - density on - chip storage applications. Oxide semiconductor (OS) - based gain cells have been verified in both n - n and n - p configurations. The operation of the 2T - 0C gain cell is mainly determined by the charge stored at the storage node (SN) between the write/read transistors and is particularly sensitive to the capacitive coupling between the write word line (WWL) and the SN. The ultra - low leakage characteristics of n - type OS transistors make them ideal candidates for write transistors because they can effectively maintain the charge at the SN in the standby state. On the other hand, due to the weaker capacitive coupling effect, p - type channels are more suitable as read transistors than n - type channels, providing a larger sensing window for read operations.
Although n - type OS technology is relatively mature, the research progress of p - type OS materials is still limited and challenging. In recent years, tin monoxide (SnO) has become a widely studied p - type oxide semiconductor candidate material due to its good thermal compatibility (up to about 350 °C), tolerance to hydrogen, and unique electronic structure. In this material, the valence band is formed by the overlap of O - 2p and Sn - 5s orbitals, thus supporting p - type transport. However, to fully realize the potential of SnO as a read transistor in gain cell applications, several challenges still need to be addressed, including: (1) improving mobility and reducing contact resistance to improve the on - current; (2) reducing hysteresis to achieve a stable threshold voltage; and (3) realizing adjustable threshold voltage and a higher ION/IOFF ratio to reduce leakage current and sneak - path current, which is crucial for expanding the storage array and integrating more cells on each bit line. Previous proof - of - concept studies have successfully demonstrated back - gated SnO transistors fabricated by physical vapor deposition (PVD) with a laboratory - scale device fabrication process. Figures 8(a) - (d) show the ID - VG curves, GI - XRD, and TEM results of typical SnO devices, indicating that the devices have good crystalline quality and the extracted mobility is about 2 cm²/V·s.
On this basis, this paper further reports the latest results of fabricating SnO devices using a foundry - compatible process flow. Figure 9(a) shows the ID - VG curve of a long - channel (LG = 1 μm) SnO device fabricated in a 300 mm wafer process, with an ION/IOFF ratio of about 10⁴, a mobility of about 1 cm²/V·s, and a hysteresis of less than 500 mV. These devices were fabricated using a back - gate process. First, a metal was deposited on the wafer as the back gate, followed by the deposition of a high - k dielectric by ALD, and then SnO was deposited by PVD. After defining and isolating the channel region by active etching, a layer of SiO₂ was deposited as the inter - layer dielectric (ILD).
Table II: Performance benchmark comparison of 1T OS devices.
Finally, source/drain (S/D) contacts were formed by contact etching in the ILD, metal filling, and chemical mechanical polishing (CMP). Notably, these devices showed good uniformity across the 300 mm wafer (see Figure 9(b)). Despite these positive developments, further exploration and optimization in materials and process development are still needed to fully unlock the potential of SnO - based devices.
The deposition parameters for fabricating SnO by PVD (such as oxygen partial pressure Opp% and total pressure) are crucial for suppressing the formation of undesirable tin oxidation states (such as Sn or SnO₂), whose presence may lead to unfavorable metallic or n - type transport behavior. Figure 10 shows the VT - ION relationship of SnO transistors under different Opp% and total pressure conditions, indicating that these parameters have a significant impact on the thin - film quality and device behavior. The results suggest that there may be percolation transport in SnO, a phenomenon also common in n - type OS, but further research is needed to fully clarify the dominant transport mechanism in this material system. Two methods were adopted for source/drain contact optimization of p - type OS transistors: (1) reducing the Schottky barrier (SB) height by reducing the surface trap - state density at the contact/SnO interface; (2) increasing the local carrier concentration in the source/drain regions to improve the band bending and reduce the tunneling width. Figure 11 shows the significant modulation of the contact resistance with the gate voltage, reflecting the characteristics of Schottky contacts. Through contact optimization, about a 5 - fold reduction in RC was achieved.
1T OS - FeFET with high endurance
Ferroelectric field - effect transistors (FeFETs) using Hf₁₋ₓZrₓO as the ferroelectric layer are considered promising candidates for high - speed, low - power storage due to their electric - field - driven writing mechanism. Both the oxide semiconductor channel and the ferroelectric dielectric can be deposited by ALD, which provides the feasibility for realizing high - density, three - dimensional storage with excellent cost scalability. However, integrating ferroelectric materials with oxide semiconductor channels introduces some unique challenges to the operation of OS - FeFET memories. The main problems include: (1)