RISC-V China Summit Kicks Off! On-site Real Shot of RayCore Highlight D35: When RISC-V Meets Data Stream, The New Answer for Domestic AI Chips
At Camellia Hall C05, 5th Floor, Shenzhen Convention & Exhibition Center (Futian), Corex invites you to experience the power of "China's Core" on site
On October 19, the 2026 RISC-V China Summit officially kicked off in Shenzhen.
As the highest-spec RISC-V industry event in China, this summit has gathered almost all core players in the RISC-V ecosystem at home and abroad. Turing Award winner David Patterson, Andrea Gallo, CEO of RISC-V International, and representatives from all major domestic RISC-V chip enterprises were present at the event.
The theme is also very intriguing: "Eve of Large-Scale Commercial Adoption".
An obvious signal is that RISC-V is no longer just a technical topic in the community. It is moving from the laboratory to the industry, evolving from "functional" to "high-performance and user-friendly".
At this grand event, the booth of a Chinese company is worthy of special attention: Suzhou Corex.
The booth is located at Camellia Hall C05, 5th Floor, and we will give you a sneak peek first.
On-site Coverage: Full House Right After Opening
On the first day of the summit, there was an endless stream of visitors at Corex's booth.
According to on-site staff, less than two hours after the venue opened in the morning, most of the hundreds of prepared brochures had been distributed.
Two highlights attracted the most attention:
The first one is the physical Highlight D35 chip itself.
The Highlight D35 chip, placed in the center of the booth, features 128GB of large video memory and Chiplet packaging. Many visitors squatted down to take a closer look and took photos with their mobile phones.
The other one is the plaque of "Intel Global Procurement Approval".
There was almost always a crowd around this plaque, and industry developers and engineers were all asking the same question: "How did your core pass Intel's verification?"
After all, the RISC-V circle is not large, and industry insiders have a clear judgment on the performance of core IP. Being admitted to Intel's global procurement system is not a marketing gimmick, but a solid proof of strength.
A technical director from a local Shenzhen chip company talked at the scene for nearly half an hour, and one of his remarks was quite thought-provoking:
"In the past, domestic RISC-V products were generally considered to be mid-to-low end MCUs. Now when we see a high-end AI chip like the Highlight D35 that can run large models locally with a self-developed core, it is truly a different story."
Why does Corex deserve serious attention at the RISC-V Summit?
To be honest, there are many domestic companies engaged in RISC-V research, but Corex's technical path is truly unique.
Most companies are working on "RISC-V + traditional AI acceleration", while Corex is developing "RISC-V + dataflow".
What is the difference between these two paths?
Traditional AI chips adopt the von Neumann architecture: data is stored in memory, moved to the computing unit for calculation, and then moved back after the computation is completed. 80% of the power consumption is actually spent on "moving data" rather than "calculating data". This is what people often call the "memory wall".
The dataflow architecture is a completely different idea: Where the data is, the computation takes place. When data flows into the chip, the operation is triggered automatically without instruction scheduling.
This fundamentally bypasses the power consumption black hole of "data movement". That is why the energy efficiency ratio of the dataflow architecture in AI inference scenarios can be several times higher than that of similar competing products.
RISC-V provides the dataflow architecture with an open, independent and controllable instruction set foundation.
One solves the problem of "how to compute more efficiently", and the other solves the problem of "what instruction set to use for more independent control".
The combination of the two forms a full-stack technical path of "architectural innovation + independent instruction set".
This is also the core differentiation of the Highlight D35: it is not just another RISC-V AI chip, it is the world's first mass-produced RISC-V dataflow physical AI chip.
It did not emerge out of nowhere, but is the result of 20 years of dedicated effort.
Many people hear about Corex for the first time, but this team has been deeply engaged in the field of processor architecture for 20 years.
The team leader, Dr. FAN Dongrui, participated in the architecture design of Loongson 1, 2 and 3 in his early years, and presided over the R&D of multiple domestic processors including Godson-X and the 64-core Godson-T. In 2011, the Godson-T many-core processor was named one of the top ten global events in the server field by *Microprocessor Report*, and it was the only academic chip selected that year.
In 2007, FAN Dongrui went to the United States to study under Professor GAO Guangrong (one of the earliest ACM/IEEE dual Fellows in Chinese mainland), and began to delve into the "non-mainstream" dataflow path.
After returning to China, the Corex team continued to move forward along the dataflow path, 20 years, one single path. They are one of the earliest teams that have gone the farthest on the dataflow track in China.
As for RISC-V technology, it has been a determined path for Corex since its establishment, with more than 10 years of technical accumulation. The Highlight D35 today is not built out of thin air, but the result of the Corex team's long-standing technical accumulation coming to fruition.
Corex is the first domestic company whose self-developed RISC-V IP has obtained procurement approval from a global chip giant.
Mass Production Is Not the End, Ecosystem Is the Real Battlefield
The theme of this summit is "Eve of Large-Scale Commercial Adoption", and Corex has already taken the lead in commercial implementation.
The Highlight D35 has been deployed in multiple fields including embodied intelligence, video intelligence, smart parks, cabin-driving integration, satellite and communications. Its revenue reached 67 million yuan in the first year of commercialization in 2023, exceeded 100 million yuan in 2024, and achieved break-even in 2025.
The more critical point is the ecosystem:
• On the software side, the full-stack toolchain has been fully connected: CUDA-compatible compiler, Triton support, model library and inference engine are all ready for developers to use immediately.
• In terms of large model adaptation, mainstream models such as Qwen 7B/35B and Minimax H3 have all been successfully run.
In terms of policy, the 15th Five-Year Plan has clearly listed RISC-V, dynamic sparse computing and edge inference chips as key priority areas. The direction that Corex has been deeply engaged in for many years is perfectly aligned with the national strategic rhythm.
From chips to solutions, from hardware to software, from technology to ecosystem — the Highlight D35 is answering the question "How far can RISC-V+AI go" with its full-stack capabilities.
You Are Welcome to Visit Us On Site
If you are attending the RISC-V China Summit in Shenzhen, you are welcome to stop by Corex's booth at Camellia Hall C05, 5th Floor:
• Check out the physical Highlight D35 and the details of its Chiplet packaging
• Talk with our technical team about RISC-V cores, dataflow architecture, adaptation and migration, and other related topics
• Directly connect with our team if you have cooperation intentions
Exhibition Period: October 19-20
Booth: Camellia Hall C05, 5th Floor, Shenzhen Convention & Exhibition Center (Futian)
RISC-V has offered China's chip industry an opportunity to "change tracks".
However, changing tracks does not equal overtaking. In the end, we still have to rely on excellent products and ecosystem to win the competition.
The Highlight D35 has presented a new option.
RISC-V + dataflow may be the exact path to achieve overtaking through track changing.
Corex — the definer of dataflow RISC-V intelligent architecture, the leader in physical AI chips.