Vertical power supply has become a new rising star.
The large AI models continue to drive the rapid performance improvement of computing power chips. To achieve higher computing throughput, the overall power consumption of AI chips has increased significantly, while the internal power supply voltage of chips keeps decreasing. According to the power formula P=U×I, the voltage drop will further push up the operating current. At APEC 2026, power vendors have taken 3000A as the design target in the next-generation power supply reference platform, while the lateral board-level power supply that has been used for many years is hitting the physical ceiling. Faced with a series of practical contradictions caused by high current, such as loss, space occupation and transient response, Vertical Power Delivery (VPD) has become the next-generation power supply architecture that the industry is focusing on promoting.
The urgent demand at the technical level has also been quickly transmitted to the industrial end, and related capital movements have become intensive accordingly. In May 2026, ADI acquired Empower Semiconductor, and in August, Infineon acquired C2i Semiconductors and Navitas acquired Claros. The completion of three large transactions in just a few months has sent a strong industrial signal: vertical power supply is no longer just technical pre-research by niche vendors, and leading global analog semiconductor enterprises have all entered the market to place bets. This power supply architecture change forced by AI computing power has truly entered the stage of industrial practical operation.
Traditional Power Supply Can No Longer Keep Up
Over the past decade, AI servers have widely adopted lateral board-level power supply solutions. This architecture can well adapt to CPUs and early GPUs, but with the sharp surge in power consumption and current of AI chips, the shortcomings of the original design have been fully exposed.
The traditional lateral power supply arranges voltage regulation devices around the GPU chip, and transmits power to the chip core through the copper foil traces on the motherboard. Since the core voltage of the GPU has dropped to 0.6-0.8V and the current is as high as thousands of amperes, according to the I²R power consumption law, the greater the current, the loss on the power supply path will be amplified in square order.
According to the data publicly released by TSMC at the APEC conference, the resistance of the PDN (Power Delivery Network) of the traditional board-level power supply network is about 90-140μΩ, with significant path loss; after switching to vertical power supply, it can be reduced to 10-15μΩ, and the loss is reduced by about 89%. The industry estimates accordingly that this part of path loss can account for 20% to 30% of the total power supply of the whole machine, and the loss converted into heat will directly push up the power usage efficiency and long-term operation cost of the data center.
Space conflicts are also unavoidable. Today's AI chips are surrounded by HBM memory, and the PCB area left for power supply components around the package is very limited. Looking back at NVIDIA's GPU iterations, from V100 to B200, the number of GPU power supply phases has increased from 16 to more than 60. The way of simply increasing the number of power supply phases and piling power devices on the board has reached the physical boundary.
Source: NVIDIA/TIPMPP21887|APEC 2026 Presentation Report
In addition to power consumption and space, violent load fluctuations also bring troubles to traditional power supply. During the training and inference of large models, the chip load changes extremely fast, and the long traces bring high parasitic inductance, so the power supply response cannot keep up with the load jump, which is prone to voltage drop and affects the chip to run at full computing power stably. The industry has tried methods such as thickening copper foil, upgrading TLVR inductors, and increasing the number of power supply phases, but these are all repairs within the existing system and cannot solve the root problem of long-distance traces.
It is these practical constraints that prompt the industry to turn its attention to the new system of vertical power supply.
Different from lateral power supply that delivers power from the side of the chip, the core idea of vertical power supply is to move the voltage regulation unit from the side of the chip to directly under the chip, so that the current is supplied vertically upward to the chip core, compressing the power supply path from centimeter level to millimeter level, thereby reducing the impedance and parasitic inductance of the power supply network. According to the integration depth, the industry divides it into different stages: PCB-VPD (back vertical module), SIVR (voltage regulator embedded in the package substrate), and In-Package IVR (voltage regulation circuit integrated into the chip package), which together form the near-chip power supply technology pedigree.
Source: Collated by Semiconductor Industry Observer
The benefits brought by this architecture change are very clear. The test results from Vicor's official white paper show that vertical power supply can reduce the resistance of the power supply network to 5-7μΩ, and the power distribution loss can be reduced by up to 95%; after the power supply path is shortened, the transient response capability is significantly improved, which can match the rapidly fluctuating load of AI chips. The front side of the motherboard no longer needs to place a large number of power devices, and the space can be reserved for HBM and high-speed interconnection to adapt to the increasing integration of chips. Of course, vertical power supply is not without cost. Module layout, packaging process and BOM cost will all bring new engineering challenges.
Vertical Power Supply Moves from Concept to Industrialization
Looking back at the development history of vertical power supply technology, Intel completed the R&D of FIVR (Fully Integrated Voltage Regulator) technology as early as 2012, and it was officially mass-produced with the Haswell processor in 2013, integrating the voltage regulator into the CPU package, which is an important engineering practice of IVR technology. As for the vertical power supply for AI chips, Vicor officially announced a cooperation with Kyocera in 2019, with Kyocera providing organic packaging, substrate and motherboard integration, to jointly develop a new generation of co-packaged power solutions for AI and high-performance processors. But at that time, it was mainly based on scheme cooperation and verification, and no large-scale mature products for AI accelerators had been formed.
It was not until the power consumption and current of AI chips rose rapidly and the old architecture became unsustainable that vertical power supply ushered in a real industrialization opportunity, and gradually differentiated into several practical and feasible technical routes.
Among them, PCB-VPD is the fastest advancing solution at present. The power module is directly welded on the back of the processor motherboard, and the chip package does not need to be redesigned, which can be compatible with the existing server supply chain, and the transformation pressure of the whole machine manufacturers is the smallest. SIVR, on the other hand, represents the medium and long-term evolution direction, aiming to integrate the voltage regulation circuit on the chip carrier, with a shorter path and better performance than the former. However, SIVR requires deep collaboration among chip, substrate and power vendors, and the supply chain is more complex.
In-Package IVR is theoretically the solution with the best performance, where voltage regulation and silicon capacitors are directly embedded into the chip package, resulting in the shortest power supply path. But at the same time, it has strict requirements for packaging yield, heat dissipation and device reliability. At this stage, it is more oriented to high-end customized computing power, and mass production still requires continuous process optimization.
The three routes have their own trade-offs, and there is no situation where one technology completely dominates in the short term, and they will iterate in parallel. But it is certain that after the demonstration of leading chip vendors and the prototype testing of cloud vendors, vertical power supply is no longer just a laboratory concept, and has become an important development direction of the next-generation high-end AI servers.
Global Industrial Layout of Vertical Power Supply
Chip vendors are at the top of the industrial chain. Relying on the power consumption, current and packaging layout requirements of AI chips, they directly determine the technical parameters, architecture selection and commercialization pace of vertical power supply, and are the core demand traction party of the whole track.
As the core leader of the global AI computing power platform, NVIDIA takes the lead in uniting partners across the whole industrial chain to promote the systematic collaborative adaptation of the new-generation power supply architecture. According to the 800V DC architecture white paper officially released by NVIDIA, the company clearly plans to implement the 800V high-voltage DC power supply system around 2027, build a new power supply infrastructure adapted to 1MW-level AI racks, and pave the way for ultra-high density AI clusters. At the same time, the Rubin architecture equipped with high-density HBM4 has clear layout constraints, making VPD the most feasible technical solution.
Google, AMD and Intel have also made layouts in advance. CapitalG, under Alphabet (Google's parent company), once invested in Empower Semiconductor, a high-end IVR chip enterprise, and public papers confirmed that the TPU platform is facing the problem of high-current power supply, and it continues to explore near-chip power supply technology. For the next-generation 3kW-level high-power consumption AI accelerator, AMD has carried out internal VPD scheme verification, focusing on optimizing PDN loss, electromigration and whole-machine heat dissipation. Intel, on the other hand, continues to build on the accumulated FIVR integrated voltage regulation technology, and advances both PCB-VPD and in-package IVR routes in parallel to adapt to the iteration requirements of server CPUs and AI acceleration chips.
After the chip end puts forward system requirements, power supply, analog and passive component vendors will undertake the implementation of hardware solutions. As a representative vendor of global high-performance and high-density power modules, Vicor laid out the VPD technical solution very early, launched the vertical power supply prototype with Kyocera in 2019, and launched the back-of-board mounted AI power module relying on the fractional power supply architecture, which greatly reduces the PDN impedance and has served many leading AI customers.
ADI, as a major analog chip manufacturer, has a mature and complete server board-level analog power product line, but lacks the core devices of IVR integrated regulators and silicon capacitors for near-chip scenarios. To this end, ADI acquired Empower Semiconductor to obtain FinFast IVR and ECAP silicon capacitor technologies, filling the short board of the power supply link from cabinet input to chip core.
For Infineon, it has successively launched the OptiMOS TDM series PCB-VPD power hardware modules since 2024. To further supplement the software and system capabilities required for the evolution of vertical power supply to the substrate integration route, it announced the acquisition of C2i Semiconductors, an Indian power management startup, on August 24.
Coincidentally, almost at the same time, Navitas also officially announced the proposed acquisition of Claros, an AI power management startup. Navitas said it will supplement the complete set of near-chip power supply technologies for processors through mergers and acquisitions, and combine its own high-voltage device advantages to open up the complete power supply chain from the power grid to the xPU core.
In addition, many other vendors have also launched corresponding products and solutions based on their own technical accumulation. For example, MPS has released an ultra-thin ZPD vertical power supply module, which is adapted to liquid-cooled servers and deeply participates in the development of whole-machine prototypes; TDK has launched stackable high-current back-of-board power modules, providing standardized component solutions; Delta focuses on system-level customization, deeply cultivating cloud vendors' VPD whole-machine solutions and 800V power supply ecosystem.
On the whole, vertical power supply has become a strategic track that power semiconductor vendors must seize, but the industry has not yet formed a unified interface and system standard, and the technical game and ecological construction of the industrial chain are still continuing to advance.
Dilemma and Future of Vertical Power Supply
Even if the industry is generally optimistic about vertical power supply, moving from prototype testing to large-scale volume production still needs to cross several hurdles of technology, supply chain, cost and ecology.
At the engineering level, PCB-VPD places the power module on the back of the motherboard, and the downward heat dissipation of the chip overlaps with the heat generated by the power module itself, which brings great challenges to the thermal design of the whole machine; back device welding, temperature cycling and long-term vibration put forward higher requirements for server reliability verification, and the whole machine needs to invest a long time for testing. In terms of cost, high-density power modules, special capacitors and inductors, customized PCBs and substrates will all raise the BOM cost. For inference servers and general data centers that are sensitive to cost, the incremental cost is an unavoidable practical problem.
In terms of technical routes, PCB-VPD, SIVR and IVR have their own advantages and disadvantages, and no overwhelmingly optimal solution has emerged. Many vendors dare not put all their resources on one single route. There are also obvious shortcomings at the ecological level. At present, there are no unified industry specifications for VPD interfaces, mechanical dimensions and test methods. Chips, power supplies and ODMs are doing their own things, resulting in fragmented solutions and increased adaptation costs for the whole machine. For cloud vendors, they need to weigh the new hardware investment against the TCO benefits brought by long-term power saving. At this stage, they are more willing to carry out small-scale pilots on high-end training servers, and will not directly replace the existing mature architectures on a large scale.
But the general trend of computing power upgrading will not change, and vertical power supply will be implemented in stages. At present, it will be preferentially implemented in high-value scenarios such as high-end AI training servers and HPC supercomputers, and complete prototype introduction and business verification in the form of PCB-VPD, while general servers and mid-to-low-end inference servers will still use the mature lateral power supply architecture. With the continuous iteration of AI chips and the gradual maturity of supporting power devices and substrate processes, the scale effect is expected to gradually dilute the incremental hardware cost, and vertical power supply will further penetrate into mid-range inference scenarios. The industry will also complete a round of technical route screening, and some hybrid compromise solutions may get more implementation opportunities. Current industry organizations such as OCP have started discussions on related topics, which are expected to promote general interface specifications in the future. At the same time, capital mergers and acquisitions occur frequently, and the market pattern tends to further concentrate.
From a longer-term perspective, the design idea of vertical power supply is not limited to AI GPUs. With the expansion of demand for high-power computing hardware, this power supply concept will also spill over to fields such as high-performance ASICs, high-end FPGAs and industrial supercomputers, and become an important technical option for high-power computing hardware.
Conclusion
Computing power competition is no longer only about the chip itself. Power supply has changed from a system supporting solution in the past to a key base that restricts the release of computing power. The vertical power supply solution is no longer a simple upgrade of a single component, but a full-chain transformation of chips, power ICs, magnetic devices, PCB substrates and whole machine systems. The successive mergers and acquisitions launched by ADI, Infineon and Navitas are essentially the giants competing for the market initiative of the next-generation AI power supply architecture. Therefore, the popularization speed of vertical power supply solutions will also directly affect the evolution trend of AI computing power infrastructure in the future.
This article is from the WeChat official account "Semiconductor Industry Observer" (ID: icbank), author: Xia Xue, published with authorization from 36Kr.