The Next Five Years of AI Chips: Will the Wafers Still Be Round?
As the size of AI chips continues to increase rapidly, a tricky shape paradox is becoming increasingly prominent: high-end computing power chips tend to be large and square, while the packaging substrates that serve as carriers still follow the traditional circular design. This is not only an inherent limitation due to physical characteristics but also an established paradigm that the semiconductor industry urgently needs to break through.
01 The "Geometric Account" of the Transition from Circle to Square
Before that, we need to understand why wafers are round while chips are square.
The rotational pulling in the Czochralski process determines the cylindrical shape of the silicon ingot, which in turn determines that the wafers are circular. In the Czochralski process, high-purity silicon is first heated to a molten state in a crucible. Then, a seed crystal is placed at the end of a precisely oriented rod, and the end is immersed in the molten silicon. After that, the rod is slowly pulled upward and rotated. Through precise control of the pulling rate, rotation rate, and temperature, a large cylindrical single-crystal silicon rod can be obtained at the end of the rod. Subsequently, after processes such as grinding, polishing, and cutting of the silicon rod, a usable circular silicon wafer can be obtained.
Chips are arranged in a square pattern on the wafer, and cutting only needs to be done along straight lines, which is efficient and results in less waste. If the chips were circular, the cutting process would be more complex and time-consuming. Square chips are easier to align with leads or pads during the packaging process, especially when using Flip chip packaging, where the square design facilitates machine operation.
Firstly, there is the problem of material waste. When cutting square chips from a traditional 12-inch circular wafer, a large amount of unutilizable waste is generated at the edges, and the area utilization rate is usually less than 85%. In contrast, panel-level packaging with a rectangular path can easily achieve an area utilization rate of over 95%. This "de-cornering" design significantly increases the number of chips that can be produced in a single process. According to industry estimates, when transitioning from wafer-level packaging to panel-level packaging, the unit cost is expected to be reduced by 20% to over 30%.
Secondly, there is the rigid size limitation. With the accelerating technological complexity at the sub-20nm node, the semiconductor manufacturing cost has increased rapidly. Transitioning the wafer size from 300mm to 450mm is one of the solutions to this problem, but the corresponding substrate size cannot meet the continuously expanding packaging requirements of AI chips.
More importantly, there is the risk of out-of-control warping. During the high-temperature packaging process, large-sized circular substrates are prone to warping and deformation due to uneven stress distribution, which can lead to signal transmission interruption. In contrast, square substrates can control the warpage within a lower range through a regular structural design, fully meeting the precision requirements of advanced packaging.
02 The Battle for "Square" Dimensions: Two Mainstream Routes
Currently, there are two major technical branches in fan-out packaging: fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP). Among them, FOWLP is based on circular wafers for packaging, while FOPLP uses square panels as substrates.
According to the Yole report, the area utilization rate of FOWLP technology is less than 85%, while that of FOPLP is greater than 95%. FOPLP can accommodate more chips and is also cheaper than FOWLP. The cost of panel-level packaging will be reduced by 66% compared to wafer-level packaging.
The world of square substrates is far more than just FOPLP.
TSMC's CoPoS technology also evolved from the "panelization" of CoWoS 2.5D packaging. It is fundamentally different from FOPLP. FOPLP does not have an interposer and is mainly used in mature processes such as power management and sensors. The full name of CoPoS is Chip-on-Panel-on-Substrate. The core of CoPoS technology lies in mounting the chip module on a panel-level substrate for packaging. By using a larger-sized square panel, the area utilization rate can be improved, and at the same time, it supports larger packaging sizes. This is crucial for future ultra-large AI GPUs, AI ASICs, and HPC chips. Next-generation AI chips need to integrate more computing dies and more sets of HBM, and the size limitations of traditional packaging will gradually fail to meet the requirements, while CoPoS can precisely break through this bottleneck.
In the fields of AI, HPC, power electronics, and even aerospace, a fierce battle over "shape, material, and performance" has already reached a white-hot stage.
Let's first look at square silicon substrates. They are made of high-purity single-crystal silicon. The greatest advantage is that their coefficient of thermal expansion is almost exactly the same as that of the chips, so the warpage is extremely small, and high-density through-silicon vias can be integrated on them. As early as 2024, Mitsubishi Materials announced that it could produce 600mm×600mm square silicon substrates specifically for ultra-large AI chips. However, their disadvantages are high cost and great difficulty in large-size production.
Next, let's look at glass substrates. Glass substrates rely on excellent material properties such as low coefficient of thermal expansion, high flatness, and low dielectric loss. When combined with TGV glass through-hole interconnection technology, they can fully leverage the advantages of large-size panel processes and effectively solve problems such as warping, insufficient wiring density, and high high-frequency signal loss in traditional packaging substrates. This is currently the most popular material in the industry, and both Intel and TSMC are heavily investing in it.
Ceramic substrates represent a completely different technical route. They are usually made of alumina, aluminum nitride, or silicon carbide. The biggest highlight is their ultra-high thermal conductivity - the thermal conductivity of aluminum nitride can reach about 170 - 230W/m·K. At the same time, they are resistant to high voltage and corrosion and can operate reliably in extreme environments for a long time. Their drawback is that they are fragile in large sizes, and the cost is also higher than that of organic substrates.
If FOPLP has brought the "square" into the mainstream view of packaging, it is actually these substrate materials that carry circuits, transmit signals, and dissipate heat that truly determine the future performance, size, and cost of chips.
03 Square Substrates: Being Rushed to Patent by Giants
It is reported that TSMC is fully promoting the next-generation panel-level packaging technology, CoWoS. The current key R & D specification is 310×310 mm, and it is evaluating the integration of glass materials on this size. Roland Rettenmaier, the Chief Sales Officer of German equipment manufacturer SCHMID, pointed out that the entire industry is gradually moving towards standardization, and the mainstream panel sizes include 310×310 mm, 510×515 mm, and 600×600 mm, among others. The 310×310 mm specification that TSMC is focusing on promoting this time is to find the best balance among packaging area, production yield, and equipment compatibility.
As early as after the launch of TSMC's InFO, ASE began investing in the R & D of fan-out panel-level packaging, aiming to provide advanced packaging solutions with lower unit costs. After long-term technological research, ASE has overcome key problems such as panel warping and made significant progress. ASE initially trial-produced FOPLP with a 300×300 mm specification and achieved a good yield. Currently, it has advanced the panel specification to 600×600 mm and believes that if the yield of 600 mm products meets expectations, customers will introduce them. At that time, 600×600 mm is expected to become the mainstream specification for FOPLP. According to the explanation of ASE's Chief Operating Officer Wu Tianyu in February 2025, the trial production of this production line will be completed by the end of 2025, and samples will be sent to customers for product certification starting in 2026. This means that ASE will officially accept customer orders in 2026 and provide commercial panel-level packaging services to the market.
According to TrendForce, AMD has contacted ASE to discuss packaging PC processors using FOPLP, and Qualcomm has also discussed using FOPLP for power management ICs with ASE.
Innolux has also mastered the ultra-large panel packaging process and is currently the producer of FOPLP with the largest panel size in the industry. Innolux's FOPLP panel size is as large as 700mm×700mm, far exceeding the common 300 - 600 mm specifications of other manufacturers. Innolux has launched the second-phase capacity expansion. The monthly production capacity of the trial mass production line is about 1,000 ultra-large panels, and samples have been sent to many domestic and overseas customers for verification. Market sources indicate that Innolux has received orders from European IDM giants NXP and STMicroelectronics. In terms of applications, Innolux has entered the fields of consumer electronics and automotive electronics for mature process chips.
Powertech Technology is also one of the first OSAT manufacturers to invest in FOPLP. As of 2025, Powertech has completed the construction of panel-level packaging capacity and has taken the lead in entering the mass production stage. The industry points out that Powertech, ahead of TSMC and ASE, has jointly carried out small-scale production of new FOPLP products with international IDM giants. Although its current contribution to revenue is limited, as the advanced packaging market develops towards panel-level, Powertech is expected to quickly expand new business opportunities.
Nvidia is also paying attention to FOPLP technology. As early as 2024, market rumors said that Nvidia was interested in introducing FOPLP packaging technology in the Blackwell architecture chips for use in GB200. However, there has been no relevant update since the release of GB200.
In addition to packaging technology, the advancement of glass substrate technology has also become a focus of attention.
In September 2023, Intel announced the launch of the industry's first glass substrate for next-generation advanced packaging, with a plan to start mass production from 2026 to 2030. Intel has invested about ten years in glass substrate technology and is the first company to develop a glass substrate solution.
As early as CES 2024, Samsung Electro-Mechanics proposed to establish a glass substrate prototype production line, aiming to produce prototypes in 2025 and achieve mass production in 2026. Industry insiders said that Samsung Electro-Mechanics has selected equipment suppliers for the glass substrate pilot line, including Korean companies Philoptics, Jungwoo, and overseas companies Chemtronics and LPKF.
Absolics, a subsidiary of the South Korean SK Group, has invested $600 million and plans to build a glass substrate factory with a monthly production capacity of 4,000 pieces in Covington, Georgia. SK Hynix has entered this field through this US subsidiary. BOE in China has established glass substrates as a core strategy and plans to achieve mass production of high-aspect-ratio products in 2027...
04 How Many Hurdles Does the Square Substrate Still Need to Cross?
Although square substrates show theoretical advantages in terms of space utilization and material loss control, they have absolutely no possibility of replacing the mainstream position of circular substrates in the short term.
After decades of industrial development, circular substrates have formed a complete and mature supporting system from single-crystal growth, cutting and polishing to lithography and thin-film deposition. The equipment, processes, and testing standards are all deeply optimized around the circular geometric shape. This huge industrial inertia and ecological stickiness are extremely difficult to break. If square substrates want to shake the position of circular substrates, they must face several core problems that have not yet been overcome.
Firstly, the stress distribution at the edges of square substrates is much more complex than that of circular substrates. They are prone to warping and cracking during high-temperature processes, which directly affects the yield.
Secondly, the existing mainstream manufacturing equipment, such as spin coaters and circular plasma etching chambers, is all based on axisymmetric design. Changing to square substrates requires a revolutionary transformation of the core chambers and even the entire production line layout, with a huge investment scale and unknown risks.
Finally, there is still a lack of mature and stable engineering solutions for the handling, positioning, and mask alignment accuracy control of square substrates at the mass production level, and problems such as fragmentation rate and uniformity are prominent.
Overall, although a few leading enterprises and research institutions have carried out pilot projects in the fields of compound semiconductors or advanced packaging, it may take at least five more years to truly solve the full-chain problems from material growth to equipment compatibility and then to yield improvement.
This article is from the WeChat official account "Semiconductor Industry Insights" (ID: ICViews). Author: Feng Ning. Republished by 36Kr with permission.