Achieving automation in chip design verification and boosting development efficiency by over 10 times, ZW Semiconductor completes tens of millions of yuan in angel round financing | 36Kr Exclusive

From the rapid rise of the chip industry in the capital market to Huawei's release of the "Tao (τ) Law", driven by the AI wave, the semiconductor industry, which is booming, has entered a super cycle, driving the upstream industrial chain such as chip design to experience an explosion in demand.

However, with the sharp increase in demand, the design complexity continues to increase, and the excessively long chip verification cycle has become an increasingly obvious bottleneck that drags down the development rhythm. A research report by Siemens and the Wilson Research Group in 2024 pointed out that the risk of tape - out for high - process complex chips is very high, and the success rate of the first tape - out is only 14%. "It generally takes about two years for a chip to go from architecture to tape - out, and the manpower and time consumed in the verification stage often exceed 60%." Wang Xi told 36Kr.

Digital chip development process

Wang Xi is the founder and chairman of "Zhiwei Chuangxin". Currently, he is also an associate professor and doctoral supervisor at Southeast University. In 2025, Wang Xi's team, relying on the previous technological accumulation at the National Innovation Center for Integrated Circuit Design Automation Technology (EDA National Innovation Center), officially founded Zhiwei Chuangxin, committed to solving the dilemma of improving the efficiency of the chip design verification stage.

In May 2025, the team launched "ChatDV", the world's first large - model intelligent agent product for the digital chip verification field, covering high - frequency links such as test generation, assertion generation, reference model construction, and automatic debugging. It has increased the chip development efficiency by more than 10 times, reduced the cycle by 50%, and cut the cost by 33%. Currently, the team has cooperated with several companies such as CETC Group, Xinhuazhang, Qingwei Intelligence, and Weina Hexin, achieving commercial implementation.

36Kr learned that recently, Zhiwei Chuangxin has completed an angel - round financing of tens of millions of yuan. This round of financing was led by Guozhong Capital, followed by Shixi Capital and Miracle Plus. Fangchuang Capital served as the financial advisor. The funds will be mainly used to deepen the core technological barriers, meet the computing power requirements, and cover the company's daily expenses.

The core team of Zhiwei Chuangxin comes from Southeast University, Tsinghua University, and City University of Hong Kong. It consists of high - level scientific research and engineering talents in the fields of integrated circuits, EDA, and large models, with the capabilities of original technological breakthroughs, industrial implementation, and ecological resource integration. Founder Wang Xi is a high - level talent in Jiangsu Province's "333" Program and a Xiaomi Young Scholar, who has long been deeply involved in agile chip development; Co - founder Jiang Zhe is a professor at the School of Integrated Circuits of Southeast University and a high - level young talent in the country, focusing on the intelligent verification closed - loop of integrated circuits; Co - founder Wang Xinze is from the Turing Award Laboratory of Tsinghua University, under the tutelage of Turing Award winner Academician David Patterson, focusing on the engineering implementation of AI large - model training and verification intelligent agents. The team is also supported by experts such as Professor Guan Nan, the deputy director of the Department of Computer Science at City University of Hong Kong, and Professor Yang Jun, the executive director of the EDA National Innovation Center, in terms of cutting - edge technology, industry - academia - research cooperation, and industrial implementation.

Build an "AI large model + data flywheel" process, increasing chip development efficiency by more than 10 times

In 2023, Wang Xi's team, then at Tsinghua University, tried to use GPT - 3.5 to generate a 40,000 - gate RISC - V processor and successfully taped it out, winning the second place in the first Efabless AI Design Contest. "This made us believe that it is feasible to automatically generate chips with the help of AI large - model tools." Wang Xi said. "However, when communicating with customers, we found that what they care about is not how fast the code is written, but whether the accuracy can be guaranteed and whether the tape - out will fail due to design flaws."

For a long time, chip design verification has been a typical labor - intensive task, highly dependent on engineers' repetitive manual work such as writing test cases, debugging errors, and generating verification codes. It is also the main reason for chip development delays and cost overruns.

Traditional EDA tools and large models are difficult to truly replace manual labor. Jiang Zhe analyzed to 36Kr, "EDA tools are better at deterministic analysis, but design verification requires understanding highly professional scenarios such as design specifications, hardware codes, test platforms, assertions, simulation logs, and coverage." General large models can only complete language and code generation at present. They lack the knowledge and experience of chip verification and solutions for continuous interaction with chip - field tools, and cannot be deployed locally.

Therefore, Zhiwei Chuangxin chose the technical route of "AI for EDA". Relying on a large amount of self - owned code and verification experience accumulated in the fields of chip architecture and design, a large amount of high - quality data is generated and labeled through the training of large models and other toolchains, forming a sustainable data flywheel to provide fuel for the continuous iteration of the model. Thus, an automatic verification process without manual review item by item is established.

In this closed - loop verification process, data is the fundamental factor restricting the capabilities of large models. Most of the high - quality data such as hardware codes, test platforms, and assertions in the chip industry are closed - source and stored in the internal networks of various companies. The public data on the Internet is scarce in quantity and uneven in quality, mostly simple codes for teaching purposes. "So data is our real moat." Wang Xi said.

Currently, the ChatDV intelligent agent has achieved module - level AI design and verification automation, covering four verification links: writing tests, writing rules, finding problems, and building models. According to Jiang Zhe, ChatDV is not a single - point tool but an intelligent platform that includes multiple toolkits and covers various high - frequency tasks in the verification process. The ultimate goal is to significantly reduce the working time of chip verification engineers.

Schematic diagram of ChatDV toolkits and working principles

Among them, the iTest module is responsible for automatically generating TestBench and test stimuli. For an RTL module of about 5,000 lines, traditional manual work requires about 1.5 person - months of effort, while ChatDV only takes 10 minutes under the condition of sufficient GPU computing power; the iSVA module can automatically generate SystemVerilog assertions (SVA), which are the "rule checkers" inside the chip, and can shorten the development cycle of complex assertions from 3 days to several hours; the iModel module automatically generates a reference model (Golden Model) for functional comparison, with a pass rate 1.69 to 4.89 times higher than that of general SOTA large models; the iDebug module automatically locates and fixes errors based on simulation error information, with a repair rate of 89%. In complex scenarios, the repair rate can be up to 4.28 times higher than that of general SOTA large models.

The above four modules together form a complete verification closed - loop: the large model is responsible for generating content, and tools such as simulators and compilers are responsible for verifying the correctness and feeding the results back to the model for iteration. Jiang Zhe compares this closed - loop to "connecting hands and feet (toolchain) to the brain (large model)."

Example of ChatDV running interface

In Wang Xi's view, the relationship between Zhiwei Chuangxin and traditional EDA manufacturers is complementary rather than competitive. EDA manufacturers are better at physical design links such as synthesis, placement, and routing in the back - end of chip design, while Zhiwei Chuangxin focuses on the front - end logic, including from specification definition, architecture design, RTL generation to functional verification, filling the gap of the lack of automation tools in the front - end.

"The rapid growth of Zhiwei Chuangxin cannot be separated from the incubation support of the EDA National Innovation Center in terms of computing power resources, early R & D costs, and talent team building." Wang Xi added. The EDA National Innovation Center is the only national - level innovation center in the domestic EDA field, focusing on disruptive innovation technologies from scratch, which is highly consistent with the concept and route of Zhiwei Chuangxin.

Welcome the arrival of the chip AGI era with "one - click chip generation"

Currently, the team has reached cooperation with several chip companies, such as CETC Group, Qingwei Intelligence, and Weina Hexin, and is also in trial cooperation with several GPU and NPU manufacturers.

In terms of business model, Zhiwei Chuangxin provides a variety of service forms: large enterprises with their own computing power resources can deploy the Agent large model locally and be charged by license; small and medium - sized enterprises are suitable for configuring "hardware + software" all - in - one machines to solve the problem of insufficient computing power; design services can provide customized IP verification services or IP development for customers.

In addition, ChatDV has launched a free - trial education version product, and dozens of enterprise customers have participated in the trial and feedback. Wang Xi said that launching the free - trial version also helps the company cultivate user habits and build brand awareness.

Wang Xi said that the automation of chip module - level verification represented by ChatDV is only the first step for Zhiwei Chuangxin to achieve its ultimate vision - "one - click chip generation". On this basis, the team is currently conducting research and development on IP - level automatic verification. ChatCPU has achieved an 11 - stage pipeline for a 4 - issue out - of - order multi - issue processor, with a complexity of more than 4 million gates, and has discovered more than a dozen functional "bugs" in the two classic RISC - V processor chips, BOOM and Rocket, which have been taped out multiple times and were not previously detected manually. In the next three years, Zhiwei Chuangxin plans to successively achieve subsystem - level intelligent generation and SoC - level one - click tape - out.

"The revolution in the chip industry will not occur or be avoided due to personal wishes. We hope to be the company that unveils the curtain at the beginning of the AGI era of digital chips." In Wang Xi's view, in the future, the demand for chips will be highly fragmented, and automation, low cost, and agile development will no longer be just icing on the cake, but a necessity for chip companies. The idea of Zhiwei Chuangxin to embrace the chip AGI era is to use AI to design better chips and then feed back to accelerate AI training and inference, forming a positive flywheel.

"If this flywheel can start spinning, the AGI era of chips may really arrive, and the industry will be completely restructured. It's still hard to determine the specific form of the industry in the future, but it has shown enough imagination to look forward to." Wang Xi said.