Another HBM killer is exposed.

In recent years, HBM has become one of the most attention - grabbing keywords in the semiconductor industry. With the continuous explosion of demand in AI large models, high - performance computing, and data centers, HBM, with its advantages of ultra - high bandwidth and low power consumption, is rapidly becoming an indispensable core technology for high - end computing power chips, thus triggering a new round of competition in the storage industry.

However, at the same time, the development of HBM also faces significant challenges. Whether it is the process complexity, yield, and cost pressure brought by advanced packaging, or issues such as heat dissipation, power consumption, and production capacity supply, all are testing the collaborative ability of the entire industrial chain. Against the backdrop of the continuously rising demand for AI computing power, those who can break through these bottlenecks first will have the opportunity to take the initiative in the next - stage competition.

Moreover, due to the huge market, HBM has attracted many challengers. Recently, Intel and SoftBank, through its subsidiary Saimemory, have launched a new assault on HBM.

Is Intel Making a Comeback?

It is a well - known fact that Intel was once a pioneer and leader in the DRAM industry. However, later, under the pressure of Japanese enterprises, they abandoned the DRAM business and turned to CPUs, which has made it the current blue giant. This time, with the popularity of artificial intelligence, they seem eager to try. It is reported that Saimemory, in which they are involved, has been developing a technology to replace the currently popular high - bandwidth memory (HBM), aiming to provide higher bandwidth and capacity for the memory modules used in powerful AI accelerators.

SAIMEMORY is a subsidiary established by SoftBank in December 2024, aiming to commercialize next - generation memory technologies. Through this cooperation, SAIMEMORY will leverage Intel's technical expertise to advance the research and development of next - generation memory architectures and manufacturing technologies. This includes the next - generation memory basic technologies established by Intel's "Advanced Memory Technology (AMT)" program (supported by the US Department of Energy) and the technical knowledge demonstrated through the "Next - Generation DRAM Bonding (NGDB) program".

Intel's expertise in the DRAM field will be applied to the development of ZAM. However, a SoftBank spokesperson said that ZAM "is similar to an advanced DRAM and will adopt brand - new technologies". The name ZAM comes from the concept of the "Z - axis". Although the technical details have not been announced, the spokesperson said, "We are considering adopting a vertical stacking structure."

Regarding AMT, in January this year, Joshua Fryman, then the Chief Technology Officer of Intel's Government Technology, said, "Intel's Next - Generation DRAM Bonding program demonstrates a brand - new memory architecture and a revolutionary assembly method, which can significantly improve DRAM performance, reduce power consumption, and optimize memory costs. The standard memory architecture cannot meet the needs of artificial intelligence. Therefore, NGDB defines a brand - new method to accelerate our progress towards the next decade."

Currently, systems using high - bandwidth memory often sacrifice the performance of other indicators (such as capacity) in exchange for higher bandwidth. The NGDB technology eliminates most of the trade - offs between high - bandwidth and double - data - rate DRAM, while significantly improving energy efficiency. Therefore, NGDB enables more types of applications and systems to take advantage of high - bandwidth memory.

Under this program, a new stacking method and a new DRAM organizational structure have been developed. The initial prototype verified that this new assembly method can overcome the memory capacity limitations of existing technologies, and the latest prototype demonstrated a functional DRAM using the new stacking method. The demonstration confirmed that the NGDB technology can be combined to produce high - performance and mass - producible memory.

At the VLSI conference to be held in June 2026, Saimemory plans to publish a paper on its newly developed HB3DM memory.

It is reported that this memory is based on Z - Angle Memory (ZAM) technology. ZAM refers to the vertical (Z - axis) stacking method of chips, similar to traditional HBM. However, Intel aims to achieve excellent performance using the most advanced manufacturing technologies. The first - generation HB3DM will adopt a nine - layer structure and use hybrid bonding technology for 3D chip layout. The bottom layer is a logic layer for managing data transmission inside the chip, and the upper eight layers are DRAM layers for data storage. Each layer contains approximately 13,700 TSVs (Through - Silicon Vias) for hybrid bonding.

In terms of capacity, each layer of HB3DM can provide approximately 1.125 GB of capacity, which translates to 10 GB per memory module. Intel can achieve a memory bandwidth of approximately 0.25 Tb/s per square millimeter of the chip. Therefore, for a 10 - GB module with a chip area of 171 square millimeters, we can expect the bandwidth of each module to be approximately 5.3 TB/s. These astonishing figures may quickly surpass the competing HBM4 memory because HB3DM offers higher bandwidth. The single - stack speed of HBM4 is approximately 2 TB/s, less than half of that of HB3DM.

However, the capacity of HB3DM is limited, currently only 10 GB, while the single - stack capacity of HBM4 can reach up to 48 GB. With the progress of HB3DM technology, Intel may increase the number of layers of mass - produced chips. But for now, it has become the leader in the bandwidth field.

Currently, we do not know when Saimemory will launch these memory chips, nor do we know who will manufacture the underlying DRAM. However, due to Intel's involvement, Intel's foundries may resume DRAM production, although the specific process node is not yet clear.

As the 2026 Very Large Scale Integration (VLSI) conference approaches, we expect Intel and SoftBank to announce more information about their subsidiary Saimemory and its progress. Saimemory plans to complete the prototype product in early 2028 and launch commercial products in 2029.

The Real 3D DRAM Enters the Arena

If you are familiar with HBM, you know that this high - bandwidth memory is achieved through a stacking method, which seems similar to 3D DRAM.

However, in fact, although both HBM and 3D DRAM are related to "3D stacking", they are not the same concept. HBM is essentially a high - bandwidth storage product for scenarios such as AI and high - performance computing. Through multi - layer DRAM stacking, TSV, and advanced packaging technologies, it significantly improves data bandwidth and energy efficiency. On the other hand, 3D DRAM is more of a next - generation DRAM underlying technology route, aiming to break through the traditional two - dimensional scaling bottleneck and improve storage density through a vertical structure to continue Moore's Law.

Therefore, the industry is exploring the use of 3D DRAM to replace HBM, and NEO Semiconductor is one of the pioneers.

On April 23, NEO Semiconductor announced that its 3D X - DRAM technology had successfully passed the proof - of - concept (POC), proving that a new type of high - density DRAM can be manufactured using the existing 3D NAND infrastructure.

The core of this release is the company's 3D X - DRAM technology, a new type of DRAM designed to break through the limitations of traditional memory expansion by adopting a vertical stacking architecture, thereby achieving higher density, lower power consumption, and better suitability for AI - driven workloads.

NEO's 3D X - DRAM architecture draws heavily on 3D NAND manufacturing technology. According to the company, the proof - of - concept chip is manufactured using a mature 3D NAND process, including existing equipment and materials. This is crucial because one of the main constraints in advanced memory development is not design innovation but manufacturing cost and process compatibility.

The POC test chip shows that 3D X - DRAM can be manufactured using the existing 3D NAND infrastructure, including mature equipment, materials, and cost - effective processes. Given that the mass - production layer count of current 3D NAND has exceeded 300 layers, these results pave the way for the next - generation high - density 3D DRAM while verifying its excellent electrical performance and reliability. The main results of the POC test include: read/write latency: < 10 nanoseconds; data retention time: > 1 second at 85°C (15 times better than the 64 - millisecond JEDEC standard); bit - line interference: > 1 second at 85°C; word - line interference: > 1 second at 85°C; endurance: > 10¹⁴ cycles.

It is reported that this achievement is mainly due to the design based on indium gallium zinc oxide (IGZO) - a crystalline material well - known for its application in display technology. The 1T1C and 3T0C storage cells can be stacked like 3D NAND, thereby improving capacity and throughput while maintaining energy efficiency.

Jeongdong Choe, a senior technology researcher and senior vice - president at TechInsights, said, "At this critical moment, NEO Semiconductor has made a significant breakthrough." As the scaling technology of traditional DRAM approaches its limit, the industry is turning to 3D architectures and new cell technologies to meet the growing needs of artificial intelligence and data centers. NEO's silicon - based POC (proof - of - concept) represents an important milestone, proving the practical feasibility of this technology beyond theoretical concepts. The announced electrical performance and reliability test results are encouraging, and this progress is in line with the industry's roadmap towards vertically expanding memory. Just as the transition to 3D NAND in the past decade, we are now witnessing the arrival of a new era of 3D DRAM that surpasses the traditional scaling limit. It is truly exciting to see this vision become a reality."

HBF, Already Established

In addition to the above technologies, HBF, which has a first - mover advantage, has long been one of the candidates to replace HBM.

However, we must emphasize that HBF is not intended to completely replace HBM but to complement it and jointly build a more efficient memory hierarchy. In AI inference tasks, HBM can be used to process hot data that is sensitive to latency, while HBF is suitable for storing and reading large - scale non - volatile data sets. Since the cost of NAND is lower than that of DRAM, HBF is expected to significantly reduce the expansion cost of AI systems, especially in large - scale models and edge - computing scenarios.

HBF is a next - generation flash memory concept launched by SanDisk in February 2025, and its core architecture is similar to HBM. As the core technology supporting AI computing, HBM has achieved rapid growth recently, achieving significantly higher speed (bandwidth) and performance through DRAM stacking. HBF, on the other hand, not only increases bandwidth but also capacity by stacking NAND flash memory. While HBM is a memory optimized for speed - used for real - time computing in AI training - HBF maximizes capacity. Different from DRAM, NAND can retain data without power supply (non - volatile), so it has attracted much attention as a new storage solution for AI.

Since the basic organizational principle of HBF draws on the high - bandwidth chip stacking and parallel interface design of HBM and adapts them to the non - volatile, page - oriented characteristics of modern NAND flash memory, this technology has the following features:

Chip stacking and Through - Silicon Vias (TSV): The HBF package consists of multiple vertically stacked 3D - NAND chips, and each chip is connected to the controller base chip through TSV. The base chip is manufactured using a logic process and integrates all channel controllers, error - correction (ECC), wear - leveling engines, and PHY circuits for high - speed parallel transmission;

HBM - type host interface: The package exposes hundreds to thousands of pins, and each pin supports multi - Gb/s signal transmission. Its PHY and pin arrangement are the same as those of HBM and can be directly connected to the existing HBM controller on the accelerator or use its variants through the CXL or PCIe interface;

DDR synchronous flash I/O: At the chip and channel levels, high - bandwidth signal transmission is achieved through a double - data - rate (DDR) synchronous interface. All data transmissions are carried out on the rising and falling edges of the data valid strobe (DVS) signal and coordinated by an on - chip delay - locked loop (DLL). This architecture keeps the traditional flash pin arrangement unchanged, thus ensuring backward compatibility and package - size compatibility;

Channel interleaving: The controller supports multiplexing through "channels" (each channel accesses multiple flash chips in parallel) and multi - channel striping (separate parallel buses) to expand the aggregate bandwidth to saturate the host interface;

As a new memory layer between the ultra - high - speed memory HBM and the high - capacity storage device SSD, HBF technology can bridge the gap between the high performance of HBM and the high capacity of SSD, ensuring the capacity scalability and energy efficiency required for AI inference. HBM is responsible for handling high bandwidth, while HBF technology serves as a supporting layer in the architecture. Specifically, HBF technology is expected to reduce the total cost of ownership (TCO) and improve the scalability of artificial intelligence systems. The industry predicts that the demand for complex memory solutions, including HBF, will start to grow around 2030.

In the artificial intelligence inference market, the role of companies that can provide a full - set of memory solutions including both HBM and HBF is becoming increasingly important because the system - level optimization of CPUs, GPUs, and memory determines the overall competitiveness, rather than the performance of a single chip.

However, recent news indicates that although the 4TB HBF memory stack capacity far exceeds that of HBM, NVIDIA doesn't seem interested. Reports suggest that Google has locked in the procurement channel for HBF memory, and the sample testing of HBF memory will start this year.

Considering NVIDIA's position, this casts a shadow over the future of HBF.

HBM's "Counterattack"

Facing so many challengers, HBM is also accelerating its evolution.

In May last year, KAIST, a top - tier national research institution in South Korea, released a 371 - page report detailing the development process of high - bandwidth memory (HBM) technology up to 2038, focusing on improvements in bandwidth, capacity, I/O interface width, and heat - dissipation performance. The roadmap covers various stages from HBM4 to HBM8, including improvements in packaging, 3D stacking, memory - centric architectures with embedded NAND flash, and machine - learning - based power - consumption control methods.