An undervalued giant in advanced packaging

In the past, when talking about Intel, people often said that they were lagging behind in manufacturing. However, in terms of advanced technologies, Intel has achieved good results in the past few years.

Let's rewind to September 2025. At that time, Jensen Huang, the CEO of NVIDIA, did something seemingly unreasonable - he promised to invest $5 billion in Intel. In the view of analysts, this money was not for wafer manufacturing or process technology, but for packaging.

The semiconductor company with the highest market value globally, whose GPUs power almost all artificial intelligence data centers around the world, looked at Intel (a company with a stock price near a ten - year low, a foundry division losing billions of dollars every quarter, and a Morningstar rating of "no moat") and decided to write a check large enough to acquire 4% to 5% of its equity. Later, Jensen Huang told the media that Intel has "the multi - technology packaging capability of Foveros, which is truly crucial here."

Naturally, people's first reaction was confusion. Intel? The company that has been lagging behind in process nodes for a decade? The company whose chief financial officer admitted that the committed orders from its foundry customers were "negligible"?

For decades, the only standard for measuring progress in the semiconductor industry has been transistor density. Smaller process nodes mean faster, cheaper, and more efficient chips. The success or failure of a company depends on its ability to shrink the process. Intel led in this race for 40 years but suffered a major setback around 2015, and TSMC took the leading position.

But while everyone was focused on the process node race, this happened: chips have become so complex that no single process node can perfectly meet all the functions of modern processors. CPU cores need the fastest transistors to ensure the raw clock frequency; GPU arrays need high density and high energy efficiency to handle parallel workloads; and what about I/O controllers, memory interfaces, and security engines? They can hardly get any improvement from cutting - edge transistors, and even so, their manufacturing costs are still incredibly high. At the 3nm process, the cost of designing a single chip exceeds $500 million.

Imagine building a house. You can use structural steel to build the entire frame of the house, including closets and garden sheds. Or, you can use steel only in key areas (load - bearing walls) and use wood elsewhere. The effect is the same, but the cost is much lower. This analogy fits well with chip - based design: use the most advanced (and most expensive) process nodes only for components that really need them, and use cheaper and more mature process nodes to manufacture all other components.

Therefore, the question is not who has the best transistors, but who can best integrate heterogeneous silicon from multiple sources into a single usable product.

How Chips Stopped Being Flat

Before delving into Intel's specific technologies, you need to master three concepts. It only takes about ninety seconds to understand them, but they will lay the foundation for you to understand all the subsequent content.

Concept 1: Chiplet

A chiplet, as the name implies, is a small chip with a single function, designed to be connected to other small chips within the same package. Instead of using a single large silicon chip to handle all functions like traditional single - chip designs, it splits the design into multiple functional modules, such as CPU modules, GPU modules, I/O modules, and memory controller modules. Each module can be manufactured using the process node most suitable for its function and then assembled together.

Concept 2: 2.5D and 3D Packaging

Chiplets need to communicate with each other. In 2.5D packaging, chiplets are arranged side by side on a shared substrate and connected horizontally through micro - bridges. Intel calls its version EMIB. You can think of it as building adjacent houses and connecting them with covered corridors. In 3D packaging, chiplets are stacked vertically, facing each other. Intel calls this Foveros. It's like building apartment floors upstairs, with elevator shafts connecting the floors. The connections are shorter, denser, and faster, but the engineering difficulty is greater due to the reduced heat dissipation space.

Concept 3: Hybrid Bonding

In the past, the method of connecting stacked chips was to use tiny solder balls called micro - bumps. Imagine dipping the bottom of a Lego brick in solder and then pressing it onto another brick. Although this method works, using solder at small sizes can be messy. Hybrid bonding technology completely abandons solder. It directly contacts the copper pads on two chips and bonds them through surface chemical reactions and thermal annealing processes. Copper atoms diffuse through the interface to form a continuous metal path.

Intel's Foveros Direct technology achieves a 9 - micron pitch (about 12,000 connections per square millimeter), with a power consumption of less than 0.05 picojoules per bit. The power consumption of in - chip communication is about 0.1 picojoules per bit. Hybrid bonding technology has crossed a critical point, making inter - chip connections as efficient as internal connections within a single chip in practical applications.

This will completely change the way chip design is calculated.

Five Generations of Updates in Seven Years

Since 2018, Intel's Foveros technology has gone through five generations of development. Each generation has addressed specific limitations of the previous generation, ultimately achieving a 30 - fold increase in interconnection density and a 3 - fold increase in energy efficiency.

The original Foveros (in 2020, Lakefield) was a proof - of - concept: 50 - micron solder micro - bumps, about 400 bumps per square millimeter, and a power consumption of 0.15 picojoules per bit. It bonded a 10 - nanometer computing chip face - down to a 22 - layer I/O chip. Although it functioned properly, this way of powering the chips caused interference, limiting further reduction of the pitch.

Foveros Omni (in 2023, Meteor Lake architecture) solved this problem through the Omni - Directional Interconnect (ODI) technology, which powers the chips through copper pillars around the substrate. You can think of it as adding external fire exits, leaving the internal stairwells only for pedestrians. This decoupled design makes it possible to mix and match chips from different foundries. The chip pitch has been reduced to 36 microns and is moving towards 25 microns.

Foveros Direct (expected to be produced at the Clearwater Forest factory in the first half of 2026) has achieved a generational leap: using copper - to - copper hybrid bonding technology, with a pitch of 9 microns, an interconnection density of over 12,000 per square millimeter, and a power consumption of less than 0.05 picojoules per bit. The goal for the second - generation product is to achieve a 3 - micron pitch (about 111,000 per square millimeter) around 2027 - 2028. Intel claims that its fluid self - alignment mounting technology can increase throughput by 10 times.

Two cost - optimized variants complete the product portfolio: Foveros - R (a cheaper RDL interposer) and Foveros - B (RDL plus a local silicon bridge), both targeting production around 2027.

Panther Lake: Four Processes, Two Factories, One Package

Theory is good, but product launch is the key. Intel's Panther Lake processor of the Core Ultra 3 series will start shipping at the end of 2025 and be fully available in January 2026. It integrates chips from four different process nodes of two foundries into a single package.

Why distribute GPU production to two foundries? Economic factors force us to do so. TSMC's N3E chips can provide higher density and efficiency when handling larger - scale parallel workloads. It is reported that Intel is not competitive in the cost of large - sized chips, but these small GPU chips can serve as a learning platform for Intel's foundry GPU manufacturing experience. The end result is that more than 70% of the chip area of Panther Lake is independently developed by Intel, which is very different from the situations of Lunar Lake and Arrow Lake.

This is the real - world embodiment of the hybrid architecture concept. Each function uses the best node, regardless of its developer.

The Math That Makes Single - Chip Structures Obsolete

Assuming a defect rate of 0.1% per square millimeter of the chip, the yield rate of a 100 - square - millimeter chip is about 90.5%, while that of a 400 - square - millimeter chip is only about 67%. At the 5 - nanometer process, for an 800 - square - millimeter single - chip SoC, the defect cost accounts for more than 50% of the total manufacturing cost.

Clearwater Forest takes this logic to the extreme: 12 small Intel 18A chips (24 cores each) are hybrid - bonded to 3 base chips, plus 2 I/O chips. A total of 17 chiplets, each of which can be tested individually before assembly.

The I/O module can be reused across different product generations. Clearwater Forest reuses the Xeon I/O module. Panther Lake offers different GPU configurations on the same platform. AMD demonstrated this with the MI300A and MI300X: on the same packaging platform, the CPU chip was replaced with a GPU chip.

Intel's Fab 9 factory in Rio Rancho, New Mexico, is the only high - capacity factory in the United States capable of mass - producing 3D advanced packaging chips. Currently, chips manufactured at TSMC's Arizona factory must be shipped to Taiwan for packaging. Mark Gardner, a vice - president at Intel, confirmed that Intel has "directly ported products using TSMC's CoWoS technology to our Foveros technology without any design changes."

Yield, cost, speed, and supply - chain resilience all favor decentralization. Together, they form a structural moat.

When 47 Tiles Come Together in One Package

Foveros is responsible for vertical stacking, and EMIB is responsible for horizontal connection. A single slot can achieve a memory bandwidth of over 5TB/s and petaFLOPS - level AI performance.

Three competitors each have their own advantages.

TSMC dominates in terms of production capacity. The CoWoS chips are expected to reach a production capacity of 80,000 pieces per minute by the end of 2025, with a target of 130,000 pieces per minute by the end of 2026. NVIDIA accounts for about 60% of the share. The SoIC hybrid bonding technology has been shipping since 2022, with a 3 - to 4 - year lead in production capacity.

AMD uses TSMC's product portfolio but also bears the risk of relying on a single supplier. The density of V - Cache is 200 times that of 2D chips. The MI300 is an accelerator with 153 billion transistors. However, AMD is completely dependent on a single supplier.

Samsung lags behind in deployment. It has not yet launched a commercial 3D hybrid - bonded logic chip. Its goal is to achieve a process below 4 microns in 2026. Its foundry market share is only 5.9%, while TSMC's is as high as 35.3%.

Packaging serves as an entry point for foundries.