The mass production of 2nm chips has been realized. TSMC has quietly "turned the table", leaving Samsung and Intel in a panic.

TSMC has quietly initiated the mass production of its 2nm chips, marking the official entry of the advanced chip manufacturing process into the 2nm era and kicking off a new round of semiconductor technology competition.

TSMC has started mass-producing its 2nm process chips!

Without a grand product launch, TSMC simply mentioned it quietly on the technology introduction page of its official website:

TSMC's 2nm (N2) technology has entered mass production as scheduled in the fourth quarter of 2025.

This simple statement represents a major breakthrough in the physical limits of semiconductor technology. It marks that TSMC's 2nm process has entered the mass production stage, and the global technology has stepped into a new era of 2nm chips.

According to TSMC's official introduction, its N2 technology adopts the first-generation nanosheet transistor technology.

Compared with the already excellent N3E process, the N2 technology has achieved significant improvements in performance and power consumption across the entire node:

At the same power consumption, the performance (speed) is improved by 10% - 15%.

At the same speed, the power consumption is reduced by 25% - 30%.

This means that our smartphones, the huge computing power driving the AI world, and all future smart devices are about to undergo a performance revolution.

Fab 22 in Kaohsiung, Taiwan, is the production base for TSMC's 2nm process.

Previously, TSMC had repeatedly stated that its N2 chips would enter mass production as scheduled in the fourth quarter of 2025, which means this plan has now been fulfilled.

From "Fin" to "Sheet": Breaking Through the 3nm Limit

All changes start from the most microscopic structure.

In the past decade, from 22nm to 3nm, the chip industry has relied on a key technology called "Fin Field-Effect Transistor" (FinFET).

You can imagine it as a series of upright "fins". The current flows through the channels formed by these fins, and the gate wraps around it from three sides, controlling the on and off of the current like a hand.

This structure has been very successful and has supported the exponential iteration of Moore's Law.

However, as the process approaches 3nm, the physical limit has arrived:

The "fins" have become thinner and thinner, and the leakage current is like an unplugged hole, making it increasingly difficult to balance power consumption and performance.

TSMC's N2 process adopts a brand - new revolutionary technology - the Gate - All - Around (GAA) nanosheet transistor.

If the FinFET controls the current from "three sides", the gate of the GAA nanosheet transistor can completely wrap around the entire current channel from "four sides".

This structure changes the original current channel from the upright "fins" to horizontally stacked "nanosheets". The gate can "embrace" the channel from all four sides, and the benefits are obvious.

First, it reduces power consumption.

Due to the improved electrostatic control, it can more precisely command hundreds of millions of transistors to "turn on" or "turn off", greatly reducing leakage current and fundamentally reducing power consumption.

Second, it can achieve stronger performance in a unit space.

This stacked nanosheet structure allows engineers to fit more transistors in the same space, ultimately increasing the transistor density.

Compared with the design of pure logic circuits, the transistor density of the N2P (an extension of the N2 series) process is about 20% higher than that of the previous N3E process.

This indicates that the chips can become smaller or integrate more powerful functions at the same size.

In addition, N2 has added Super - High - Performance Metal - Insulator - Metal (SHPMIM) capacitors to the power supply network.

According to TSMC's public information and media reports, the capacitance density of SHPMIM has more than doubled compared with the previous generation, and the Rs/Rc has been reduced by about 50%, thereby improving power stability, performance, and overall energy efficiency.

The GAA nanosheet transistor is responsible for "throttling" at the source, and the SHPMIM capacitor is responsible for "expanding sources" for performance. The combination of the two has achieved a double leap in the performance and power consumption of the N2 process.

An Ambitious Mass Production Blueprint: Fighting on Two Fronts, Aiming at AI and the Future

TSMC has chosen two locations for the mass production of its N2 process: Fab 22, a new factory in Kaohsiung, Taiwan, and Fab 20, which is adjacent to its Global R & D Center in Hsinchu, Taiwan.

Expanding production in two locations simultaneously shows TSMC's aggressive layout in advanced - process chips.

Normally, the capacity ramp - up of a new process starts with mobile chips with relatively mature technology and smaller sizes, and progresses step by step.

However, this time, TSMC has chosen to expand the production capacity of advanced - process chips in two new wafer fabs in Kaohsiung and Hsinchu.

These advanced - process chips are likely to serve multiple fields such as high - end smartphones and high - performance computing (AI/HPC).

This is a rare "two - front battle".

On one side are the mobile phone chips with an annual demand of hundreds of millions from giants like Apple. On the other side are the large - sized and complex - structured AI and server chips designed by customers like NVIDIA.

Simultaneously managing these two very different product lines, both of which have extremely high requirements for yield, will exponentially increase the difficulty.

TSMC CEO C.C. Wei said in the earnings conference call in October:

"The N2 project is progressing smoothly and will enter mass production later this quarter with a good yield. We expect a faster capacity ramp - up in 2026 driven by smartphones, high - performance computing (HPC), and AI applications."

What supports TSMC's confidence is the long queue of customers behind it.

According to market expectations, N2 will first meet the needs of high - end mobile phones, HPC, and AI.

From Apple's next - generation iPhone and Mac chips to NVIDIA and AMD's future AI accelerators, almost all top - tier technology giants have shown "great interest" in the N2 process. Therefore, it is imperative to start the production capacity of two wafer fabs at the same time.

Behind this grand plan, TSMC has a precise layout for the future market landscape:

Smartphones are the foundation, while AI and HPC are its biggest growth engines in the next decade.

From N2P to A16: The Decisive Battle for the Next Decade

Wei said that under a continuously strengthening strategy, TSMC will launch N2P as an extension of the N2 family.

N2P further improves performance and power consumption on the basis of N2 and is planned to enter mass production in the second half of 2026.

A16 is TSMC's next - generation advanced process for HPC/AI (closely related to the N2 family in architecture and ecosystem).

It adopts the Super Power Rail back - side power supply technology, mainly targeting complex artificial intelligence and high - performance computing processors, and is also planned to enter mass production in the second half of 2026.

From the architectural revolution of N2, to the continuous optimization of N2P, and then to the back - side power supply technology introduced in A16, TSMC's technology roadmap is clear. The mass production of its N2 process is undoubtedly a key node in the semiconductor industry.

It marks that the GAA nanosheet transistor architecture, one of the most critical technologies in the "post - Moore's Law era", has been successfully introduced into large - scale production by the industry leader.

This not only consolidates TSMC's leading position in the field of advanced - process manufacturing but also provides a solid foundation for the next - stage development of global industries relying on high - performance computing, from consumer electronics to artificial intelligence.

However, TSMC is not the only giant leading this advanced - process semiconductor competition.

When TSMC entered the 2nm (N2) threshold, its main competitors, such as Samsung and Intel, are also advancing their next - generation transistor technologies simultaneously.

In June 2022, Samsung announced the successful mass production of 3 - nanometer process chips using the GAA architecture.

As early as before TSMC, in June 2022, Samsung announced that it had taken the lead in mass - producing the GAA (Gate - All - Around) transistor architecture in its 3nm process, becoming the world's first wafer fab to commercialize GAA in advanced - process nodes.

This "head start" also reflects Samsung's technological strength and strategic determination in the competition for cutting - edge processes.

Meanwhile, Intel is introducing two key technologies, RibbonFET (GAA transistor) and PowerVia (back - side power supply), in its Intel 18A node.

It is reported that this node entered the early production stage in 2025 and is expected to gradually expand its production capacity and achieve broader commercial applications in 2026.

In October 2025, Intel CEO Pat Gelsinger personally demonstrated the Intel Core Ultra Series 3 processor wafer codenamed Panther Lake at the Ocotillo campus in Arizona. This was also Intel's first public display of a client - side chip developed based on the 18A (1.8nm - class) process node.

Although Intel's 18A and TSMC's N2 belong to the GAA generation, the former is more aggressive, while the latter is more conservative.

Intel is promoting the innovation of performance and power supply architecture with the combination of "RibbonFET + PowerVia" and is the first to apply it to high - complexity CPUs, trying to gain an early advantage in the next - generation process competition.

TSMC, on the other hand, first uses N2 for mass production to serve a large number of customers and reserves further technological breakthroughs for subsequent nodes such as N2P/A16.

The mass production of TSMC's N2 node is more like officially kicking off a new round of advanced - process technology competition centered around GAA in the post - FinFET era.

References:

https://www.tomshardware.com/tech-industry/semiconductors/tsmc-begins-quietly-volume-production-of-2nm-class-chips-first-gaa-transistor-for-tsmc-claims-up-to-15-percent-improvement-at-iso-power

This article is from the WeChat public account "New Intelligence Yuan". The author is Yuanyu. It is published by 36Kr with permission.